{"title":"一种适用于5G应用的26-42 GHz宽带、高效回退和容限驻波CMOS功率放大器架构","authors":"C. R. Chappidi, K. Sengupta","doi":"10.23919/VLSIC.2019.8778095","DOIUrl":null,"url":null,"abstract":"Future mm-Wave transmitter front-ends will need to operate in an electromagnetically complex environment that are resistant to near-field antenna perturbations (VSWR events) while operating across multiple mmWave frequency bands (28/37/39/42 GHz) and with high efficiency and linearity with spectrally efficient modulation. This is particularly difficult since these parameters (bandwidth, linearity, efficiency, and VSWR tolerance) trade off strongly with each other in a power amplifier (PA). In this paper, we present a PA architecture that exploits mutual load pulling through a multi-port network in a nonlinear fashion to achieve VSWR tolerance while demonstrating Doherty-like operation across 26–42 GHz. The PA designed in 65-nm bulk CMOS generates $\\mathrm {{P}_{sat}} \\gt 19$ dBm with $\\mathrm{PAE _{peak}} \\gt 20$% across all bands and achieves up to 3.35x and 4.84x enhancement in PAE at back-off power levels of 6 and 9.6 dB over class-A operation. In addition, the PA demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle and supports 64QAM OFDM modulation with 8 Gbps across 28-40GHz.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"31 1","pages":"C22-C23"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications\",\"authors\":\"C. R. Chappidi, K. Sengupta\",\"doi\":\"10.23919/VLSIC.2019.8778095\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Future mm-Wave transmitter front-ends will need to operate in an electromagnetically complex environment that are resistant to near-field antenna perturbations (VSWR events) while operating across multiple mmWave frequency bands (28/37/39/42 GHz) and with high efficiency and linearity with spectrally efficient modulation. This is particularly difficult since these parameters (bandwidth, linearity, efficiency, and VSWR tolerance) trade off strongly with each other in a power amplifier (PA). In this paper, we present a PA architecture that exploits mutual load pulling through a multi-port network in a nonlinear fashion to achieve VSWR tolerance while demonstrating Doherty-like operation across 26–42 GHz. The PA designed in 65-nm bulk CMOS generates $\\\\mathrm {{P}_{sat}} \\\\gt 19$ dBm with $\\\\mathrm{PAE _{peak}} \\\\gt 20$% across all bands and achieves up to 3.35x and 4.84x enhancement in PAE at back-off power levels of 6 and 9.6 dB over class-A operation. In addition, the PA demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle and supports 64QAM OFDM modulation with 8 Gbps across 28-40GHz.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"31 1\",\"pages\":\"C22-C23\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778095\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications
Future mm-Wave transmitter front-ends will need to operate in an electromagnetically complex environment that are resistant to near-field antenna perturbations (VSWR events) while operating across multiple mmWave frequency bands (28/37/39/42 GHz) and with high efficiency and linearity with spectrally efficient modulation. This is particularly difficult since these parameters (bandwidth, linearity, efficiency, and VSWR tolerance) trade off strongly with each other in a power amplifier (PA). In this paper, we present a PA architecture that exploits mutual load pulling through a multi-port network in a nonlinear fashion to achieve VSWR tolerance while demonstrating Doherty-like operation across 26–42 GHz. The PA designed in 65-nm bulk CMOS generates $\mathrm {{P}_{sat}} \gt 19$ dBm with $\mathrm{PAE _{peak}} \gt 20$% across all bands and achieves up to 3.35x and 4.84x enhancement in PAE at back-off power levels of 6 and 9.6 dB over class-A operation. In addition, the PA demonstrates strong tolerance to VSWR events with only 2 dB degradation over a VSWR 4:1 load circle and supports 64QAM OFDM modulation with 8 Gbps across 28-40GHz.