A. Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, S. Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, T. Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, D. Richmond, Zhiru Zhang, I. Galton, C. Batten, M. Taylor, R. Dreslinski
{"title":"A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS","authors":"A. Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, S. Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, T. Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, D. Richmond, Zhiru Zhang, I. Galton, C. Batten, M. Taylor, R. Dreslinski","doi":"10.23919/VLSIC.2019.8778031","DOIUrl":null,"url":null,"abstract":"This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"113 1","pages":"C30-C31"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778031","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
This paper presents a 16nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4GHz at 0.98V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881μm2 per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
