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Chemical Mechanical Polishing of Single-Crystalline Diamond Epitaxial Layers for Electronics Applications 用于电子应用的单晶金刚石外延层的化学机械抛光
IF 2.7 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-29 DOI: 10.1109/TSM.2024.3383287
Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht
{"title":"Chemical Mechanical Polishing of Single-Crystalline Diamond Epitaxial Layers for Electronics Applications","authors":"Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht","doi":"10.1109/TSM.2024.3383287","DOIUrl":"10.1109/TSM.2024.3383287","url":null,"abstract":"For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (<\u0000<inline-formula> <tex-math>$1 ~mu text{m}$ </tex-math></inline-formula>\u0000), doped epitaxial SCD layers with very low (<1> <tex-math>$4.5 mm^{2}$ </tex-math></inline-formula>\u0000 area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"190-198"},"PeriodicalIF":2.7,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140564910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks 利用人工神经网络识别 "坏邻居 "中的 "好伙伴
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-28 DOI: 10.1109/TSM.2024.3406395
Chia-Heng Yen;Ting-Rui Wang;Ching-Min Liu;Cheng-Hao Yang;Chun-Teng Chen;Ying-Yen Chen;Jih-Nung Lee;Shu-Yi Kao;Kai-Chiang Wu;Mango Chia-Tso Chao
{"title":"Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks","authors":"Chia-Heng Yen;Ting-Rui Wang;Ching-Min Liu;Cheng-Hao Yang;Chun-Teng Chen;Ying-Yen Chen;Jih-Nung Lee;Shu-Yi Kao;Kai-Chiang Wu;Mango Chia-Tso Chao","doi":"10.1109/TSM.2024.3406395","DOIUrl":"10.1109/TSM.2024.3406395","url":null,"abstract":"It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized \u0000<inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula>\u0000 window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"280-292"},"PeriodicalIF":2.3,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141188042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research Toward Wafer-Scale 3D Integration of InP Membrane Photonics With InP Electronics 实现 InP 膜光子学与 InP 电子学晶圆级 3D 集成的研究
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-27 DOI: 10.1109/TSM.2024.3382511
S. Abdi;V. Nodjiadjim;R. Hersent;M. Riet;C. Mismer;T. de Vries;K. A. Williams;Y. Jiao
{"title":"Research Toward Wafer-Scale 3D Integration of InP Membrane Photonics With InP Electronics","authors":"S. Abdi;V. Nodjiadjim;R. Hersent;M. Riet;C. Mismer;T. de Vries;K. A. Williams;Y. Jiao","doi":"10.1109/TSM.2024.3382511","DOIUrl":"10.1109/TSM.2024.3382511","url":null,"abstract":"In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (<\u0000<inline-formula> <tex-math>$15 ~mu text{m}$ </tex-math></inline-formula>\u0000).","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"229-237"},"PeriodicalIF":2.3,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140313410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy Consumption and Carbon Emission Reduction in HVAC System of a Dynamic Random Access Memory (DRAM) Semiconductor Fabrication Plant (fab) 动态随机存取存储器（DRAM）半导体制造厂（fab）暖通空调系统的能源消耗与碳减排
IF 2.7 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-22 DOI: 10.1109/TSM.2024.3379949
Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Chia-Jen Hsu;Chia-Hung Chou;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett
{"title":"Energy Consumption and Carbon Emission Reduction in HVAC System of a Dynamic Random Access Memory (DRAM) Semiconductor Fabrication Plant (fab)","authors":"Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Chia-Jen Hsu;Chia-Hung Chou;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett","doi":"10.1109/TSM.2024.3379949","DOIUrl":"10.1109/TSM.2024.3379949","url":null,"abstract":"This study focuses on energy saving for a Taiwan high-tech DRAM factory as the primary research subject. Collecting operational parameters related to various facility systems and process equipment is initially performed by using the developed energy conversion factors (ECF) calculator. Moreover, innovative fab energy simulation (FES) software has been designed by Taipei Tech. This software is designed for high-tech fab energy consumption analysis. The annual energy consumption data for fabs can be calculated. This data is then converted into carbon dioxide emissions using the power carbon emission coefficient provided by the Bureau of Energy, Ministry of Economic Affairs Taiwan. In this study, five different energy-saving strategies were proposed. The energy consumption and carbon emissions distribution were evaluated to assess the benefits of those different techniques. The findings show that among the existing operational facilities, the use of an exhaust air conditioning unit with reduced enthalpy value setting, with lowered supply air temperature, demonstrates the highest energy-saving. This technique has the potential to annually reduce carbon emissions by approximately 623,158 kg CO2 and operational costs by NT\u0000<inline-formula> <tex-math>${$}$ </tex-math></inline-formula>\u0000 6,005,764 (189,602 U.S.\u0000<inline-formula> <tex-math>${$}$ </tex-math></inline-formula>\u0000). This can reduce the overall manufacturing cost and is also beneficial for the environment.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"174-184"},"PeriodicalIF":2.7,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140203546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of Void Defects at TiN/Si:HfO2 Interface for 3-D Ferroelectric Memory 优化三维铁电存储器的 TiN/Si:HfO2 接口空隙缺陷
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-21 DOI: 10.1109/TSM.2024.3403230
Dongxue Zhao;Zhiliang Xia;Yi Yang;Meiying Liu;Yuancheng Yang;Zongliang Huo
{"title":"Optimization of Void Defects at TiN/Si:HfO2 Interface for 3-D Ferroelectric Memory","authors":"Dongxue Zhao;Zhiliang Xia;Yi Yang;Meiying Liu;Yuancheng Yang;Zongliang Huo","doi":"10.1109/TSM.2024.3403230","DOIUrl":"10.1109/TSM.2024.3403230","url":null,"abstract":"In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, which leads to tension at the outer interface of the 3D ferroelectric capacitor structure. Due to the unavoidable structural stress, it is necessary to optimize the interface bonding energy. First principles simulation revealed insufficient binding energy between titanium nitride and silicon doped hafnium oxide ferroelectric materials, while introducing an amorphous alumina interface layer can effectively improve the binding ability. Experimental verification has confirmed that using an amorphous alumina interface layer as an adhesive layer can successfully solve the interface void defects, thereby improving the ferroelectric properties in three-dimensional structures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"542-545"},"PeriodicalIF":2.3,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141149772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasma Pretreatment System for the Reduction of By-Product Particles in Semiconductor Manufacturing 用于减少半导体制造过程中副产品颗粒的等离子体预处理系统
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-20 DOI: 10.1109/TSM.2024.3402214
Se Yun Jo;Minsuk Choi;Sang Jeen Hong
{"title":"Plasma Pretreatment System for the Reduction of By-Product Particles in Semiconductor Manufacturing","authors":"Se Yun Jo;Minsuk Choi;Sang Jeen Hong","doi":"10.1109/TSM.2024.3402214","DOIUrl":"10.1109/TSM.2024.3402214","url":null,"abstract":"Titanium tetrachloride (TiCl4) is a well-known source of titanium (Ti) for the formation of titanium nitride (TiN) barrier material in the semiconductor interconnection process; however, the reaction of by-products with airborne molecules can cause unexpected pump trips and equipment breakdown from the by-product powder build-up. Plasma scrubbers are used to decompose by-products, but hydrogen chloride (HCl) and nitrogen oxides are produced during and after the process. The process mechanisms change when the temperature and applied power of the heat source change. In this paper, we study the influence of the reactor temperature and applied power to the heat source on the decomposition capacity of TiCl4 in a plasma pretreatment system (PPS). We examine the effect of the temperature and heat source power to understand the reaction mechanisms for the composition and decomposition of gaseous species with chemical reactions through simultaneous methods. We analyzed the system with computational fluid dynamics (CFD) and chemical kinetic simulation to investigate the changes of the system mechanism. Subsequently, we achieved results for the correlation between the temperature of the reactor, power applied to the heat source, composition and decomposition of species, and chemical reaction mechanisms.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"381-393"},"PeriodicalIF":2.3,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141149660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Call for Nominations: 2024 EDS Early Career Award 征集提名：2024 年 EDS 早期职业奖
IF 2.7 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-07 DOI: 10.1109/TSM.2024.3394310
{"title":"Call for Nominations: 2024 EDS Early Career Award","authors":"","doi":"10.1109/TSM.2024.3394310","DOIUrl":"https://doi.org/10.1109/TSM.2024.3394310","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"222-222"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522494","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Semiconductor Manufacturing Publication Information 电气和电子工程师学会半导体制造期刊》出版信息
IF 2.7 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-07 DOI: 10.1109/TSM.2024.3378552
{"title":"IEEE Transactions on Semiconductor Manufacturing Publication Information","authors":"","doi":"10.1109/TSM.2024.3378552","DOIUrl":"https://doi.org/10.1109/TSM.2024.3378552","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"C2-C2"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10521909","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Semiconductor Manufacturing Information for Authors IEEE Transactions on Semiconductor Manufacturing 为作者提供的信息
IF 2.7 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-07 DOI: 10.1109/TSM.2024.3378554
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2024.3378554","DOIUrl":"https://doi.org/10.1109/TSM.2024.3378554","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits 为现代集成电路开创快速安全的低 k 值二氧化硅合成技术
IF 2.7 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-07 DOI: 10.1109/TSM.2024.3374067
Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu
{"title":"Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits","authors":"Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu","doi":"10.1109/TSM.2024.3374067","DOIUrl":"10.1109/TSM.2024.3374067","url":null,"abstract":"With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"185-189"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140073978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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