IEEE Transactions on Semiconductor Manufacturing最新文献_第7页

RA-UNet: A New Deep Learning Segmentation Method for Semiconductor Wafer Defect Analysis on Fine-Grained Scanning Electron Microscope (SEM) Images RA-UNet：一种新的深度学习分割方法，用于细粒度扫描电镜（SEM）图像的半导体晶圆缺陷分析

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-27 DOI: 10.1109/TSM.2025.3546296

Yibo Qiao;Yanning Chen;Fang Liu;Zhouzhouzhou Mei;Yuening Luo;Yining Chen;Yiyi Liao;Bo Wu;Yongfeng Deng

{"title":"RA-UNet: A New Deep Learning Segmentation Method for Semiconductor Wafer Defect Analysis on Fine-Grained Scanning Electron Microscope (SEM) Images","authors":"Yibo Qiao;Yanning Chen;Fang Liu;Zhouzhouzhou Mei;Yuening Luo;Yining Chen;Yiyi Liao;Bo Wu;Yongfeng Deng","doi":"10.1109/TSM.2025.3546296","DOIUrl":"https://doi.org/10.1109/TSM.2025.3546296","url":null,"abstract":"In the rapidly evolving field of semiconductor manufacturing, the escalating complexity of integrated circuits poses significant challenges in identifying and analyzing defects, crucial for maintaining high wafer yield. Traditional approaches are hindered by the intricate nature of defect morphology and the scarcity of high-quality scanning electron microscope (SEM) data, essential for effective algorithm training. In this study, we propose RA-UNet for fine-grained SEM defect segmentation. RA-UNet adopts a U-shaped architecture that leverages residual networks for defect feature extraction, and introduces a residual architecture and a novel attention module to enhance the network’s focus on defects. To validate the effectiveness of the proposed model, we meticulously gathered and labeled a real SEM data set from a semiconductor manufacturing factory. The results demonstrate that RA-UNet outperforms existing methods in semiconductor defect segmentation, achieving an Intersection over Union (IoU) score of 71.92%. These findings highlight its potential as an effective tool for semiconductor defect analysis.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"185-193"},"PeriodicalIF":2.3,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Case Study on Sputtered Chromium Sacrificial Layer for Ti2O3 Microstructure Fabrication 制备Ti2O3微结构的溅射铬牺牲层实例研究

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3546217

Angel Regalado-Contreras;Wencel de la Cruz

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Call for Nominations for Editor-in-Chief: IEEE Transactions on Semiconductor Manufacturing 呼吁提名主编：IEEE半导体制造汇刊

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3540179

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Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on "Wide Band Gap Semiconductors for Automotive Applications" IEEE电子器件学报特刊“汽车用宽带隙半导体”征文

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3534591

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IEEE Transactions on Semiconductor Manufacturing Publication Information IEEE半导体制造学报

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3534602

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Call for Papers for Journal of Lightwave Technology: Special Issue on OFS-29 光波技术杂志：OFS-29特刊征文

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3534595

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Call for Papers for a Special Issue of IEEE Transactions on Materials for Electron Devices: "Exploration of the Exciting World of Multifunctional Oxide-Based Electronic Devices: From Material to System-Level Applications" IEEE电子器件材料学报特刊征文：“探索多功能氧化物基电子器件的激动人心的世界：从材料到系统级应用”

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3534593

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IEEE Transactions on Semiconductor Manufacturing Information for Authors IEEE半导体制造信息汇刊

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-25 DOI: 10.1109/TSM.2025.3534606

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A Warpage Prediction Model for Trench Field-Plate Power MOSFET in 300mm-Diameter Process 300mm直径沟槽场极板功率MOSFET翘曲预测模型

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-19 DOI: 10.1109/TSM.2025.3543133

Hiroaki Kato;Bozhou Cai;Jiuyang Yuan;Shin-Ichi Nishizawa;Wataru Saito

{"title":"A Warpage Prediction Model for Trench Field-Plate Power MOSFET in 300mm-Diameter Process","authors":"Hiroaki Kato;Bozhou Cai;Jiuyang Yuan;Shin-Ichi Nishizawa;Wataru Saito","doi":"10.1109/TSM.2025.3543133","DOIUrl":"https://doi.org/10.1109/TSM.2025.3543133","url":null,"abstract":"A wafer warpage prediction model for trench field-plate MOSFETs on large diameter wafers is proposed. Trench field-plate MOSFETs have deeper trenches and thicker oxides compared to conventional power MOSFETs, and the stress imbalance between the front and back of the wafer must be controlled to suppress wafer warpage in the mass-production process. Therefore, predicting wafer warpage throughout the process is a key technology from the viewpoint of process integration, and its importance is increasing with the use of large-diameter wafers. In this study, as a main process module in trench field-plate power MOSFET process, the processes of trench formation, oxidation, polysilicon deposition, and annealing were examined. The wafer warpage and Raman shift were analyzed by comparing the experiment results with simulations in a 300 mm diameter process. Based on the measured wafer warpage, anisotropic deformation of the poly silicon after annealing was suggested, and a new model considering this anisotropic deformation was developed to predict the through-process for 300 mm wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"263-269"},"PeriodicalIF":2.3,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Throughput and Quality Optimized Down-Selection of Overlay Measurement Markers for Robust Control of the Maximum Overlay Error in a Pattern Layer in Photolithography Processes 用于光刻过程中图案层最大覆盖误差鲁棒控制的覆盖测量标记的选择

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-18 DOI: 10.1109/TSM.2025.3543453

Noah Graff;Dragan Djurdjanovic

{"title":"Throughput and Quality Optimized Down-Selection of Overlay Measurement Markers for Robust Control of the Maximum Overlay Error in a Pattern Layer in Photolithography Processes","authors":"Noah Graff;Dragan Djurdjanovic","doi":"10.1109/TSM.2025.3543453","DOIUrl":"https://doi.org/10.1109/TSM.2025.3543453","url":null,"abstract":"This paper presents a metaheuristic optimization-based approach for selecting a pre-determined number of measurement markers from the set of available markers that optimizes the performance of the recently introduced robust <inline-formula> <tex-math>${mathrm { L}}^{infty }$ </tex-math></inline-formula> norm overlay control algorithm, which robustly minimizes the worst overlay error across a given pattern layer. This optimization is then used in a Design of Experiments (DOE) setting to build a tractable regression model of a customizable objective function encompassing cost effects of quality losses and throughput benefits resulting from the down-selection of markers selected for robust overlay control. Using this model, one can rapidly determine the optimal proportion of markers for any set of cost parameters, and the optimal subset forming this proportion of available markers can be down-selected to maximize performance of the resulting robust overlay controller. Overlay data and models from a semiconductor manufacturing fab were used to evaluate the newly proposed inspection and control strategy. Results clearly indicate that the novel strategic down-selection of measurement markers coupled with robust overlay control could lead to vastly improved throughputs without decreasing quality relative to what can be achieved using traditional Run-to-Run (R2R) control. Feasibility of the novel DOE-based optimization was demonstrated for two scenarios of cost-effect parameters.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"251-262"},"PeriodicalIF":2.3,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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