IEEE Transactions on Semiconductor Manufacturing最新文献_第6页

A Study on the Improvement of Safety and Efficiency of Clean Rooms in Semiconductor Factories Through Real Fire Experiments 通过真实火灾实验提高半导体工厂洁净室安全性和效率的研究

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-10 DOI: 10.1109/TSM.2024.3411662

Sanghyuk Hong;Hasung Kong

{"title":"A Study on the Improvement of Safety and Efficiency of Clean Rooms in Semiconductor Factories Through Real Fire Experiments","authors":"Sanghyuk Hong;Hasung Kong","doi":"10.1109/TSM.2024.3411662","DOIUrl":"10.1109/TSM.2024.3411662","url":null,"abstract":"The increasing number of fires in semiconductor factories requires new approaches to fire safety. It is important to study the specifics of the activities of companies that use potentially flammable materials in production, such as air filtration units, electrical cables and floor panels. The aim of the study was therefore to determine the level of fire risk in the clean rooms of these companies by means of real fire experiments. As a result, a fire risk assessment of the main combustible materials such as air filtration units, electrical cables and floor panels in the plenum room on the top floor of the cleanroom was carried out. The results of the experiment showed a low ignition propensity of the air filtration unit and limited fire propagation in the event of ignition. High calorific materials, such as fibreglass in filters, were identified as increasing the risk. Based on this, it was proposed to replace these materials with flame retardant materials and to improve the stop/fire control systems of the air filtration units. The results obtained in the study should be used for the development of technical recommendations for improving fire safety in critical premises at semiconductor factories.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"394-401"},"PeriodicalIF":2.3,"publicationDate":"2024-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling the Energy Consumption of Integrated Circuit Fab Infrastructure 集成电路制造基础设施能耗建模

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-06 DOI: 10.1109/TSM.2024.3408926

L.-Y. Liu;L. Van Winckel;L. Boakes;M. Garcia Bardon;C. Rolin;L.-Å. Ragnarsson

{"title":"Modeling the Energy Consumption of Integrated Circuit Fab Infrastructure","authors":"L.-Y. Liu;L. Van Winckel;L. Boakes;M. Garcia Bardon;C. Rolin;L.-Å. Ragnarsson","doi":"10.1109/TSM.2024.3408926","DOIUrl":"10.1109/TSM.2024.3408926","url":null,"abstract":"The bottom-up assessment of environmental impact of the fabrication of integrated circuit chips relies on accurate modeling of the operation of a high-volume semiconductor fab. In our virtual fab model, we structure fab operation in three concentric sectors: the wafer processing equipment, the generation of utilities that feeds the equipment, and the fab infrastructure that provides a suitable environment for the equipment and the workers. In this paper, we first address the correlation between process flow, wafer demand and fab dimension, which sets the scale of the virtual fab and enables global fab energy consumption estimates. Next, we describe how energy consumption calculations are performed sector-by-sector and how these evolve over the deployment of successive generations of logic nodes. In particular, we propose an original bottom-up model for fab infrastructure energy consumption that takes into account local climate dependence of a fab’s geographical location. The essence of these learnings is condensed into a normalized power consumption per manufacturing area (in kW/m2) that is deduced from our models as a function of technology maturity and location. These values form a good comparison basis with data from industry and literature.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"422-427"},"PeriodicalIF":2.3,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advances in the Thermal Study of Polymers for Microelectronics Using the Thermally Induced Curvature Approach 利用热诱导曲率法对微电子聚合物进行热研究的进展

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-06 DOI: 10.1109/TSM.2024.3410513

Benjamin Vavrille;Lionel Vignoud;Laurent-Luc Chapelon;Rafael Estevez

{"title":"Advances in the Thermal Study of Polymers for Microelectronics Using the Thermally Induced Curvature Approach","authors":"Benjamin Vavrille;Lionel Vignoud;Laurent-Luc Chapelon;Rafael Estevez","doi":"10.1109/TSM.2024.3410513","DOIUrl":"10.1109/TSM.2024.3410513","url":null,"abstract":"Thermoset resins are singular materials in the field of microelectronics. Because they exhibit a high contrast of thermomechanical properties with other integrated materials like oxides, metals or silicon, polymers can threaten the mechanical integrity of stacks. Knowing polymer properties allows manufacturers to foresee the compatibility between materials and improve chipsets reliability. At a bilayer scale, the properties mismatch between the polymer film and the silicon substrate causes an overall curvature of the wafer which evolves with temperature. By comparing the thermally induced curvature of two distinct substrates with the same film, the biaxial modulus and the coefficient of thermal expansion of the film can be determined. This method can not only check the achievement of the polymer cross-linking, but also estimates their relaxation temperatures. In this article, we present the ability of this method to, not only, measure those properties in the glassy state, but also, for the first time, in the rubbery state. We also illustrate the proficiency of this approach in detecting and characterizing two successive glassy states.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"251-259"},"PeriodicalIF":2.3,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

3-D NAND Oxide/Nitride Tier Stack Thickness and Zonal Measurements With Infrared Metrology 利用红外测量技术测量 3D NAND 氧化物/氮化物层叠厚度和区域分布

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-03 DOI: 10.1109/TSM.2024.3404475

Youcheng Wang;Zhuo Chen;Cong Wang;Nick Keller;G. Andrew Antonelli;Zhuan Liu;Troy Ribaudo;Rostislav Grynko

引用次数: 0

Observation and Suppression of Growth Pits Formed on 4H-SiC Epitaxial Films Grown Using Halide Chemical Vapor Deposition Process 观察和抑制使用卤化物化学气相沉积工艺生长的 4H-SiC 外延薄膜上形成的生长坑

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-04-30 DOI: 10.1109/TSM.2024.3395361

Yoshiaki Daigo;Keisuke Kurashima;Shigeaki Ishii;Ichiro Mizushima

引用次数: 0

Minimization of Particle Deposition on Wafers Caused by the Pressure Change in the Vacuum Chamber Through a Pressure Control Regulation Process 通过压力控制调节过程最大限度地减少真空室压力变化在晶片上造成的颗粒沉积

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-04-26 DOI: 10.1109/TSM.2024.3394008

Ching-Ming Ku;Wen Yea Jang;Stone Cheng

{"title":"Minimization of Particle Deposition on Wafers Caused by the Pressure Change in the Vacuum Chamber Through a Pressure Control Regulation Process","authors":"Ching-Ming Ku;Wen Yea Jang;Stone Cheng","doi":"10.1109/TSM.2024.3394008","DOIUrl":"10.1109/TSM.2024.3394008","url":null,"abstract":"In wafer etching, regular cleaning and maintenance of process chambers are necessary to reduce particle contamination of etched wafers during the wafer transfer process. Investigating alternative cleaning and maintenance is imperative. This study analyzed the number of particles falling onto a silicon wafer when the pressure difference within the process chamber was manipulated. We observed that rapid opening of the pressure control valve, which regulates the chamber’s pressure, caused contamination during wafer transport. This was particularly true when the change in the pressure ratio was considerable. The by-products near the side of the chamber’s pressure control valve were activated and transported. We verified this finding by adjusting the opening ratio of the pressure control valve (i.e., its degree of opening). We proposed that during the transition step of the etching process, this opening ratio can be controlled by regulating the process pressure through gas flow settings. This method could suppress the deposition of reflected particles originating from the turbomolecular pump’s pumping line on wafers, thereby minimizing the contamination of wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"340-344"},"PeriodicalIF":2.3,"publicationDate":"2024-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140798028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Virtual Metrology for Multistage Processes Using Variational Inference Gaussian Mixture Model and Extreme Learning Machine 利用变量推理高斯混合模型和极限学习机实现多级过程虚拟计量

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-04-24 DOI: 10.1109/TSM.2024.3392898

Tianhong Pan;Lu Liu;Menghu Li

{"title":"Virtual Metrology for Multistage Processes Using Variational Inference Gaussian Mixture Model and Extreme Learning Machine","authors":"Tianhong Pan;Lu Liu;Menghu Li","doi":"10.1109/TSM.2024.3392898","DOIUrl":"10.1109/TSM.2024.3392898","url":null,"abstract":"Virtual metrology (VM) is crucial for improving process capability and production yield during semiconductor manufacturing processes. However, the performance of VM deteriorates owing to the variable operating regime and the nonlinear characteristics of the process. Herein, Variational inference Gaussian mixture model (VIGMM) and extreme learning machine (ELM) are combined to solve these issues. First, variational inference is conducted on a Gaussian mixture model to determine the number of Gaussian components automatically and the corresponding operating regimes are identified. Subsequently, an extreme learning machine is developed for each operating regime to investigate the nonlinear relationship between process inputs and outputs. Finally, VM is implemented using the corresponding local ELM, which is determined based on the responsibility of the Gaussian components. The feasibility and effectiveness of the proposed methods are validated based on a numerical case and the plasma sputtering process for fabricating thin-film transistor liquid-crystal displays. The proposed VIGMM-ELM can serve as a VM algorithm for manufacturing processes with multiple stages.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"271-279"},"PeriodicalIF":2.3,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140798026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Predicting Temperature-Dependent Aging Effects and Permanent Set of Vacuum Sealing Systems in Semiconductor Manufacturing Processes 预测半导体制造工艺中与温度有关的老化效应和真空密封系统的永久集

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-04-23 DOI: 10.1109/TSM.2024.3392712

Christoph Wehmann;Ambarish Kulkarni;Feyzan Durn;Murat Gulcur;Alan Astbury

引用次数: 0

A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection 用于检测制造缺陷的 6T SRAM 中位晶体管阈值电压偏差监控方案

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-04-11 DOI: 10.1109/TSM.2024.3387050

Rui Liu;Hao Li;Zhao Yang;Guantao Wang;Zefu Chen;Peiyong Zhang

{"title":"A Threshold Voltage Deviation Monitoring Scheme of Bit Transistors in 6T SRAM for Manufacturing Defects Detection","authors":"Rui Liu;Hao Li;Zhao Yang;Guantao Wang;Zefu Chen;Peiyong Zhang","doi":"10.1109/TSM.2024.3387050","DOIUrl":"10.1109/TSM.2024.3387050","url":null,"abstract":"Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage \u0000<inline-formula> <tex-math>$({Vth})$ </tex-math></inline-formula>\u0000 deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor \u0000<inline-formula> <tex-math>${Vth}$ </tex-math></inline-formula>\u0000 Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"146-151"},"PeriodicalIF":2.7,"publicationDate":"2024-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140564825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improving the Reliability of Through Silicon Vias: Reducing Copper Protrusion by Artificial Defect Manipulation and Annealing 提高硅通孔的可靠性：通过人工缺陷处理和退火减少铜突起

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-04-02 DOI: 10.1109/TSM.2024.3378160

Won-Jun Choi;Myong Jae Yoo;Joonho Bae;Ji-Hun Seo;Churl Seung Lee

{"title":"Improving the Reliability of Through Silicon Vias: Reducing Copper Protrusion by Artificial Defect Manipulation and Annealing","authors":"Won-Jun Choi;Myong Jae Yoo;Joonho Bae;Ji-Hun Seo;Churl Seung Lee","doi":"10.1109/TSM.2024.3378160","DOIUrl":"10.1109/TSM.2024.3378160","url":null,"abstract":"Through silicon vias (TSVs) are a critical technology for manufacturing three-dimensional stacked structure of semiconductor packages by forming holes that penetrate silicon wafers and vertically interconnect multiple wafers. Typically, TSVs are created by drilling via holes in wafers and filling their interiors using copper electroplating processes. Subsequently, the wafers are exposed to high-temperature environments during the back-end-of-line (BEOL) process. However, improper copper electroplating conditions can form defects, such as voids and seams, within TSVs, while the high temperature of the BEOL process induces copper protrusion phenomena. These defects and copper protrusion degrade the reliability of TSV. In this brief, copper protrusion behavior, which is a direct cause of reliability degradation in TSVs, was mitigated by experimentally exploring the seam defects that can occur during the TSV filling process. Subsequent annealing processes were applied to remove the seam defects based on the copper-grain growth. The copper protrusion height was analyzed based on the size of the seam defects and annealing temperature. From the proposed process in this brief, the copper protrusion heights of TSVs without and with seam defects were confirmed to be 1.531 and \u0000<inline-formula> <tex-math>$1.289~mu text{m}$ </tex-math></inline-formula>\u0000, respectively, representing an improvement of approximately 15.81%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"166-173"},"PeriodicalIF":2.7,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140565020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0