IEEE Transactions on Semiconductor Manufacturing最新文献_第6页

Leading Sustainability Applications for More Responsible Logic Technology Development 引领可持续发展应用，实现更负责任的逻辑技术开发

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-08-14 DOI: 10.1109/TSM.2024.3438098

Teresa E. Bodtker;Richard A. Riley;Soley Ozer;Sanaz K. Gardner;Ryan J. Russell;Jeffrey Birdsall;Sam P. Johnson

{"title":"Leading Sustainability Applications for More Responsible Logic Technology Development","authors":"Teresa E. Bodtker;Richard A. Riley;Soley Ozer;Sanaz K. Gardner;Ryan J. Russell;Jeffrey Birdsall;Sam P. Johnson","doi":"10.1109/TSM.2024.3438098","DOIUrl":"10.1109/TSM.2024.3438098","url":null,"abstract":"The purpose of this paper is to outline the path that Intel has been taking to drive sustainable semiconductor manufacturing processes. As new sites are built to deliver Intel’s Design & Manufacturing (IDM) 2.0 strategy, we expand and grow our manufacturing output and facilities scope. To minimize environmental impact, there was focus on chemical and water usage reduction, chemical reuse, improvement of Destruction Removal Efficiencies (DRE), abatement of hazardous by-products, & innovation of novel Point of Use (POU) systems. There is also commitment to replacing fossil fuel with electrically driven alternatives and/or renewable natural gas. There has been a collective approach in the decarbonization methodology for all manufacturing emissions through technology-based innovations to reduce climate impact in global manufacturing. Intel also engages with suppliers and customers with a focus on reducing waste and wastewater emissions by leveraging technology to reduce environmental impacts on global manufacturing. There has been a focus on enabling greener circular economy strategies across the industry value chain by transforming its chemical footprint methodology. Collaboration with others to lead the way in the semiconductor sector has led to accelerating progress on reducing climate impact by advancing sustainable and green chemistry use. Intel strives to achieve renewable energy use and energy conservation across its global manufacturing operations, along with maximizing water conservation and implementing novel technologies to drive reduction in greenhouse gases.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"428-432"},"PeriodicalIF":2.3,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Centering Sustainability in Process Development Through Improved Characterization of HFC-PFC Byproducts 通过改进 HFC-PFC 副产品的表征，在工艺开发过程中注重可持续性

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-08-06 DOI: 10.1109/TSM.2024.3439271

Nathan Marchack;Eric A. Joseph

{"title":"Centering Sustainability in Process Development Through Improved Characterization of HFC-PFC Byproducts","authors":"Nathan Marchack;Eric A. Joseph","doi":"10.1109/TSM.2024.3439271","DOIUrl":"10.1109/TSM.2024.3439271","url":null,"abstract":"Recent legislation concerning the potential regulation of per- and polyfluorinated chemistries as a class (PFAS) has enormous implications for the field of semiconductor manufacturing. This is so because the material foundation of silicon and its dielectrics which prevails across all advanced device technologies dictates the usage of fluorocarbon gases, particularly for subtractive patterning and chamber cleaning processes. Simultaneously, recent progresses in artificial intelligence have spurred large investments in fabrication plants to produce the critical hardware driving that field. As these trends stand in clear opposition to each other, it is increasingly important for synergy between research fields to center sustainability as a key parameter of technological development. The first critical step for such research efforts involves improved characterization of the fluorinated byproducts created in such manufacturing processes. The use of low-temperature plasma discharges tremendously increases the complexity of the available reaction pathways, making this task significantly more challenging. In this paper we present a novel technical analysis method applied to the fluorocarbon polymerization remaining on through-silicon via sidewalls patterned using the Bosch Process. Fluorinated carbon fragments with longer chain lengths than the starting gas precursor molecule were detected, which represents to the best of our knowledge the first time this has been reported in literature. This baseline will be invaluable in future research efforts to assess novel chemistries and abatement treatments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"453-457"},"PeriodicalIF":2.3,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Achieving Sustainability in the Semiconductor Industry: The Impact of Simulation and AI 实现半导体行业的可持续性：模拟和人工智能的影响

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-08-05 DOI: 10.1109/TSM.2024.3438622

Wojciech T. Osowiecki;Martyn J. Coogans;Saravanapriyan Sriraman;Rakesh Ranjan;Yu Joe Lu;David M. Fried

{"title":"Achieving Sustainability in the Semiconductor Industry: The Impact of Simulation and AI","authors":"Wojciech T. Osowiecki;Martyn J. Coogans;Saravanapriyan Sriraman;Rakesh Ranjan;Yu Joe Lu;David M. Fried","doi":"10.1109/TSM.2024.3438622","DOIUrl":"10.1109/TSM.2024.3438622","url":null,"abstract":"Computational simulation has been used in the semiconductor industry since the 1950s to provide engineers and managers with a faster, more cost-effective method of designing semiconductors. With increased pressure in the semiconductor industry to move towards greener and more sustainable manufacturing, it is crucial to understand the impact of computational simulation and artificial intelligence on environmental sustainability, specifically reducing greenhouse gas (GHG) emissions. This paper quantifies the degree to which various types of simulation used for hardware, process, and device optimization can be adopted for different applications in wafer fabrication equipment research and development, along with the potential reduction in physical experimentation, saving silicon, gases, chemicals, and wafers. With this understanding and an estimation of the equivalent carbon cost impact of the computation itself, analyzed projects demonstrated a significant (>80%) decrease in emissions, primarily driven by the ability to use fewer patterned and blanket wafers whose carbon footprint appears to be orders of magnitude larger than that of used modeling resources. The paper concludes with an attempt to quantify the environmental savings from virtualization across our entire research organization and to illustrate the potential future impact of described activities.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"464-474"},"PeriodicalIF":2.3,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10623438","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reducing Datacenter Compute Carbon Footprint by Harnessing the Power of Specialization: Principles, Metrics, Challenges and Opportunities 利用专业化的力量减少数据中心计算的碳足迹：原则、指标、挑战和机遇

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-31 DOI: 10.1109/TSM.2024.3434331

Tamar Eilam;Pradip Bose;Luca P. Carloni;Asaf Cidon;Hubertus Franke;Martha A. Kim;Eun K. Lee;Mahmoud Naghshineh;Pritish Parida;Clifford S. Stein;Asser N. Tantawi

{"title":"Reducing Datacenter Compute Carbon Footprint by Harnessing the Power of Specialization: Principles, Metrics, Challenges and Opportunities","authors":"Tamar Eilam;Pradip Bose;Luca P. Carloni;Asaf Cidon;Hubertus Franke;Martha A. Kim;Eun K. Lee;Mahmoud Naghshineh;Pritish Parida;Clifford S. Stein;Asser N. Tantawi","doi":"10.1109/TSM.2024.3434331","DOIUrl":"10.1109/TSM.2024.3434331","url":null,"abstract":"Computing is an indispensable tool in addressing climate change, but it also contributes to a significant and steadily increasing carbon footprint, partly due to the exponential growth in energy-demanding workloads, such as artificial intelligence (AI). While hardware specialization has become the primary driver of operational energy efficiency improvements, it introduces new challenges including increased embodied emission, and a rise in complexity of operations of heterogeneous and dynamic datacenters. We posit that while specialization is necessary for sustainable computing, to fully harness its power, the academic and technical community must address the specific challenges arising from embracing it. We enumerate and analyze key challenges that specialization introduces across software, system design, and operations, and their potential impact on carbon cost, and propose a way forward for each identified area. Furthermore, we argue that intricate relationships exist across the life-cycle of compute systems, which must be understood, modeled, and analyzed to identify the most beneficial Pareto frontiers for carbon life-cycle efficiency. We analyze these trade-offs and offer an approach to address them using a unified metric and framework.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"481-488"},"PeriodicalIF":2.3,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10618912","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141870543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wafer Dicing Vibration Investigation on Novel Wafer Mounting Techniques 新型晶片安装技术的晶片切割振动研究

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-29 DOI: 10.1109/TSM.2024.3435338

Mohd Syahrin Amri;Ghazali Omar;Mohd Syafiq Mispan;Fuaida Harun;M. N. B. Othman;N. A. Ngatiman;Masrullizam Mat Ibrahim

{"title":"Wafer Dicing Vibration Investigation on Novel Wafer Mounting Techniques","authors":"Mohd Syahrin Amri;Ghazali Omar;Mohd Syafiq Mispan;Fuaida Harun;M. N. B. Othman;N. A. Ngatiman;Masrullizam Mat Ibrahim","doi":"10.1109/TSM.2024.3435338","DOIUrl":"10.1109/TSM.2024.3435338","url":null,"abstract":"Chipping has emerged as a significant issue in semiconductor manufacturing, particularly during the dicing process. The existing conventional single-sided wafer mounting technique does not have sufficient holding capability which contributes to instability during dicing and causes higher chipping performance. The objective of the study is to develop a novel wafer mounting technique that can hold the wafer firmly during dicing and improve the chipping performance. In the experiment, chipping and vibration performance during the dicing process on novel double-sided semi and full-sandwich wafer mounting were investigated and compared with the conventional single-sided wafer mounting technique. Chipping was measured using high power scope and ImageJ software while the vibration was initiated using the NI 9234 Sound-Vibration Module and SDT1-028K Piezoelectric film. Implementing extended surface tape coverage on double-sided UV mounting tape for the full sandwich wafer mounting technique resulted in superior wafer gripping during dicing and produced the lowest topside and backside wafer chipping performance. The novel double-sided full sandwich wafer mounting technique has demonstrated higher wafer holding capability, resulting in lower vibration during dicing and improved overall chipping performance","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"583-590"},"PeriodicalIF":2.3,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141873189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of Semiconductor Reverse Osmosis System Performance With Conventional and 3D Printed Feed Channels 使用传统和 3D 打印进料通道的半导体反渗透系统性能比较

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-26 DOI: 10.1109/TSM.2024.3430820

Christopher Kurth;Zhewei Zhang;Kevin Roderick;Jay Kendall Weingardt;Richard Lopez;Hwee Kiang;Peter Navaneethakrishnan;Deena Starkel

{"title":"Comparison of Semiconductor Reverse Osmosis System Performance With Conventional and 3D Printed Feed Channels","authors":"Christopher Kurth;Zhewei Zhang;Kevin Roderick;Jay Kendall Weingardt;Richard Lopez;Hwee Kiang;Peter Navaneethakrishnan;Deena Starkel","doi":"10.1109/TSM.2024.3430820","DOIUrl":"10.1109/TSM.2024.3430820","url":null,"abstract":"Semiconductor manufacturing requires a substantial amount of high-purity water generated through a complex series of treatment processes. Reverse Osmosis (RO) as the most crucial water treatment process contributes the majority of energy consumption and carbon emission in Ultra-Pure Water (UPW) preparation for semiconductor manufacturing. However, there is an opportunity to drive innovation around the current design of feed flow channel in spiral wound RO elements to promote energy efficiency and cost savings. In this study, a novel design of feed channel with 3D printed spacers was compared with conventional design of feed channel with mesh spacers regarding energy consumption. The average head pressure of 3D printed spacer was found to be 20 psi lower than mesh spacer with same permeate flow rate, which achieved a lower specific power of 0.449 kWh/m3, resulting in a 20% energy saving compared with mesh spacer. This study demonstrated that this novel channel construction with 3D printed spacer significantly improves the overall energy efficiency in RO through reduced pressure loss and increased active area, with a potential merit of decreasing the anti-scalant usage and membrane cleaning.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"458-463"},"PeriodicalIF":2.3,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10612255","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141778548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Plasma Etching Endpoint Detection in the Presence of Chamber Variations Through Nonlinear Manifold Learning and Density-Based Clustering 通过非线性积分学习和基于密度的聚类在腔室变化的情况下检测等离子刻蚀终点

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-26 DOI: 10.1109/TSM.2024.3434489

Chae Sun Kim;Hae Rang Roh;Yongseok Lee;Taekyoon Park;Chanmin Lee;Jong Min Lee

{"title":"Plasma Etching Endpoint Detection in the Presence of Chamber Variations Through Nonlinear Manifold Learning and Density-Based Clustering","authors":"Chae Sun Kim;Hae Rang Roh;Yongseok Lee;Taekyoon Park;Chanmin Lee;Jong Min Lee","doi":"10.1109/TSM.2024.3434489","DOIUrl":"10.1109/TSM.2024.3434489","url":null,"abstract":"The consistent decrease in the open ratio of wafers has spurred a demand for advanced endpoint detection (EPD) techniques to ensure accurate plasma etching in nonlinear optical emission spectroscopy (OES) data characterized by a low signal-to-noise ratio. Additionally, precise detection of endpoint is hindered by variations between plasma chambers arising from diverse issues. To address these issues, this study proposes a nonlinear manifold learning-based EPD model and a chamber condition identification framework. The EPD model demonstrates the capability to extract endpoint-related latent variables from complex nonlinear OES data. Moreover, the model exhibits the ability to generalize to larger datasets through density-based time series clustering. The chamber condition identification framework not only classifies plasma conditions but also automates the determination of the conditions for incoming new wafers. Evaluation of the proposed approach, conducted using actual OES data from multiple chambers, demonstrated that the EPD model outperformed other models which are based on diverse dimensionality reduction approaches. Furthermore, the chamber condition identification process successfully identified condition variations and accurately determined the plasma condition of new data. Moreover, conducting EPD modeling for separate conditions rather than collectively for diverse conditions demonstrated superior detection results, underscoring the importance of the chamber condition identification process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"553-566"},"PeriodicalIF":2.3,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141778550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Boundless Engineering for Yield to Cope With the Complexity of High-Volume Manufacturing 无止境的产量工程，应对大批量生产的复杂性

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-15 DOI: 10.1109/tsm.2024.3428936

Giyoung Yang, Lay Hoon Loh, Emma Greer, Xiaodong Zhang, Shivendra Pandey, Saramma Varghese, Wee Hong Goh, Jianjun Cheng, Eric Hao Guan, Angelo Pinto

引用次数: 0

Quantitative Comparison of Simulation and Experiment Enabling a Lithography Digital Twin 实现光刻数字孪生的模拟与实验定量比较

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-12 DOI: 10.1109/TSM.2024.3427409

Yutong Xie;Benyamin Davaji;Ivan Chakarov;Sandy Wen;Michael Hargrove;David Fried;Peter C. Doerschuk;Amit Lal

{"title":"Quantitative Comparison of Simulation and Experiment Enabling a Lithography Digital Twin","authors":"Yutong Xie;Benyamin Davaji;Ivan Chakarov;Sandy Wen;Michael Hargrove;David Fried;Peter C. Doerschuk;Amit Lal","doi":"10.1109/TSM.2024.3427409","DOIUrl":"10.1109/TSM.2024.3427409","url":null,"abstract":"Digital twins of the semiconductor fabrication process provide means for optimization of the physical layout and nanofabrication process design, studying compatibility between desired structures and a process flow, and a pathway to analyze the root causes of defects for state-of-the-art CMOS and MEMS devices. In this paper, a metric for the geometric differences between structures visualized by CD-SEM images is defined, and a computer-vision-based algorithm is developed to evaluate the metric. One of the major uses of such metrics is to compare experimental and simulated images. For this application, numerical results are presented when the simulator is SEMulator3D®, a physics-based process modeling software system for semiconductor and MEMS devices. Computer vision tools, such as filters, thresholding, and morphology operations, are used to extract geometric features from CD-SEM images and pattern matching and symmetric difference are used to compute the metric. Examples of using the metrics to quantify the geometric similarity between a simulated nanostructure and an experimental CD-SEM image of the fabricated nanostructure are presented. The data consists of eight classes of nanostructures which are defined, fabricated in the cleanroom with 36 combinations of layout parameters, and imaged with a CD-SEM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"546-552"},"PeriodicalIF":2.3,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141614074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111> 半导体单晶-硅生长的结构损失实时自动检测与停止规则

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-04 DOI: 10.1109/TSM.2024.3421926

Wheyming Tina Song;Yu-Fan Liao

{"title":"A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111>","authors":"Wheyming Tina Song;Yu-Fan Liao","doi":"10.1109/TSM.2024.3421926","DOIUrl":"10.1109/TSM.2024.3421926","url":null,"abstract":"The occurrence of the “structural-loss” defect during single-crystal silicon growth (SCSG) is a significant issue in semiconductor manufacturing. When structural-loss occurs, it signifies a deviation from the desired quality of single-crystal formation, leading to the need to halt the growth process. Currently, there is a lack of scholarly literature addressing the determination of an optimal stopping time to promptly halt the process upon the occurrence of the defect on-line. Our research makes a substantial contribution by addressing this gap in the SCSG process, specifically focusing on orientations <100> and <111>. The study utilizes advanced AI with YOLO-v7 and innovative approaches. These include precise annotation of crystal misorientation features through a comprehensive definition of structural-loss and novel labeling techniques, identification of optimal hyper-parameters through a robust design, and the implementation of effective stopping rule mechanisms. Significant progress has been achieved in decision-making through the implementation of the stoping time shift to terminate the SCSG process within an average of less than 3 minutes for <100> orientations (with a standard error of 0.3 minutes) and less than 5 minutes for <111> orientations (with a standard error of 0.5 minutes). The promising results indicate that the proposed approaches have the capability to substitute manual inspections, opening up possibilities for new perspectives in this particular field.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"304-315"},"PeriodicalIF":2.3,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141552962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0