IEEE Transactions on Semiconductor Manufacturing最新文献_第6页

Effectiveness of a High-Velocity-Type Laminar Air Curtain Device for Moisture Isolation Under EFEM Airflow Deflection During FOUP Door Opening 高速层流气幕装置在effem气流偏转情况下的隔湿效果

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-16 DOI: 10.1109/TSM.2026.3665224

Chi-Jen Wen;Tee Lin;Omid Ali Zargar;Chi-Huan Hsieh;Shih-Cheng Hu;Yang-Cheng Shih;Graham Leggett

{"title":"Effectiveness of a High-Velocity-Type Laminar Air Curtain Device for Moisture Isolation Under EFEM Airflow Deflection During FOUP Door Opening","authors":"Chi-Jen Wen;Tee Lin;Omid Ali Zargar;Chi-Huan Hsieh;Shih-Cheng Hu;Yang-Cheng Shih;Graham Leggett","doi":"10.1109/TSM.2026.3665224","DOIUrl":"https://doi.org/10.1109/TSM.2026.3665224","url":null,"abstract":"As semiconductor manufacturing advances toward the 3 nm node and beyond, wafer sensitivity to particulate and moisture contamination becomes increasingly critical. During front opening unified pod (FOUP) door opening, airflow disturbances and deflection from the equipment front-end module (EFEM) can lead to the intrusion of external moisture and airborne molecular contaminants (AMC), potentially degrading wafer surface integrity and process yield. To address this, a high-velocity-type laminar air curtain device (HV-LAC) was developed using a low-pressure-drop PTFE filter combined with an airflow deflector and perforated plate. This design overcomes deformation and particle-shedding issues seen in conventional ultra-high molecular weight polyethylene (UPE) panels under high flow rates, while improving flow uniformity and barrier stability. The HV-LAC achieved a maximum outlet velocity of 0.54 m/s, maintained velocity non-uniformity around 10% across all flow conditions, and met ISO Class 1 cleanliness. Performance evaluation was conducted under combinations of EFEM background velocities (0.3, 0.4, 0.5 m/s), airflow deflection angles (0°, 15°, 30°), and curtain velocities (0.35, 0.41, 0.54 m/s), with FOUP purge flow at 130 LPM. Experimental results confirmed that the HV-LAC effectively suppressed moisture intrusion, with FOUP internal relative humidity (RH) maintained below 5% in all conditions. The best isolation was observed when curtain velocity matched EFEM airflow, demonstrating that velocity matching is critical to maintaining barrier integrity. This study offers a quantitative design reference for enhancing FOUP micro-environmental control in advanced semiconductor processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"310-319"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigating the Influence of Different Diverter Pipes on the Humidity for FOUP by Using Computational Fluid Dynamics 用计算流体力学方法研究不同导流管对FOUP湿度的影响

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-12 DOI: 10.1109/TSM.2026.3664058

Yen-Hsin Chan;Jia-Sheng Du;Ming-Xian Lin;Chi-Hua Hsu

{"title":"Investigating the Influence of Different Diverter Pipes on the Humidity for FOUP by Using Computational Fluid Dynamics","authors":"Yen-Hsin Chan;Jia-Sheng Du;Ming-Xian Lin;Chi-Hua Hsu","doi":"10.1109/TSM.2026.3664058","DOIUrl":"https://doi.org/10.1109/TSM.2026.3664058","url":null,"abstract":"Maintaining a controlled environment is essential for preserving wafer quality and manufacturing yield, as humidity, oxygen, and airborne contaminants can degrade wafer surfaces during fabrication and storage. Computational fluid dynamics (CFD) simulations based on the k–<inline-formula> <tex-math>$varepsilon $ </tex-math></inline-formula> turbulence model were applied to reduce relative humidity inside a front opening unified pod (FOUP) using clean dry air (CDA) purging. A guiding duct was designed to enhance CDA circulation between wafer layers, and the influences of duct geometry and perforation configuration on flow distribution and dehumidification performance were systematically evaluated. The results indicate that increasing the number of perforations improves gas intake, while enlarging the duct diameter increases flow rate and suppresses jet effects, leading to improved flow uniformity and moisture removal. An optimized configuration combining an expanded duct with a 25-hole design achieves an average internal humidity of 3.2%, approximately 5% lower than that of a conventional cylindrical duct. These findings provide a clear direction for future FOUP design optimization and support humidity control strategies that can reduce average internal moisture levels, thereby improving process yield and enhancing production capacity in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"320-329"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Semi-Damascene FSAV: Via CD and Overlay Process Window Analysis 半大马士革FSAV：通过CD和覆盖过程窗口分析

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-02 DOI: 10.1109/TSM.2026.3659882

Yannick Hermans;Giulio Marti;Gilles Delie;Gayle Murdoch;Andrea Mingardi;Sandip Halder;Chen Wu;Seongho Park;Zsolt Tőkei

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Suppressing Hexagonal Defects in Ex Situ Remote Plasma Dry Etch Processing 非原位等离子体干蚀刻工艺中六方缺陷的抑制

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-23 DOI: 10.1109/TSM.2026.3666982

Kangjian Cheng;Jingyan Huang;Wen Siang Lew

引用次数: 0

Online Temperature Monitoring System for Semiconductor Automated Test Equipment Using Local Gaussian Process 基于局部高斯过程的半导体自动化测试设备温度在线监测系统

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-17 DOI: 10.1109/TSM.2026.3665465

Jongwon Kim;Seung Min Baik;Dahm Yu;Jaehyun Kim;Young Myoung Ko

{"title":"Online Temperature Monitoring System for Semiconductor Automated Test Equipment Using Local Gaussian Process","authors":"Jongwon Kim;Seung Min Baik;Dahm Yu;Jaehyun Kim;Young Myoung Ko","doi":"10.1109/TSM.2026.3665465","DOIUrl":"https://doi.org/10.1109/TSM.2026.3665465","url":null,"abstract":"Accurate temperature monitoring in automated test equipment (ATE) is crucial for ensuring the reliability and quality of semiconductor testing. However, ATE temperature models often rely on noisy, sparsely-sampled sensor data, and existing methods struggle to update models efficiently as operating conditions evolve. This paper presents Neighbor-Pseudo-GP, a probabilistic online method for modeling the temperature distribution of an ATE board. Our approach uses a Gaussian process (GP) to represent the entire field from a small number of observations while explicitly accounting for time-varying noise. Unlike variational methods that rely on sparse inducing points and assume homogeneous noise, we recursively merge new observations with the full posterior of the latest model under heterogeneous noise, achieving <inline-formula> <tex-math>$mathcal {O}(1)$ </tex-math></inline-formula> time and memory complexity. In addition, we design a specialized spatio-temporal kernel that clearly separates spatial and temporal effects. Experiments on synthetic data demonstrate precise estimation of time-varying noise variance and effective noise filtering. Results on semiconductor burn-in data confirm that our model reliably reconstructs the underlying temperature field, closely matches ideal sensor measurements, and adapts robustly to non-stationary conditions.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"256-265"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Transformer-Based Sequence Prediction Architecture for Etch Profile Evolution in Semiconductor Manufacturing 半导体制造中蚀刻轮廓演变的变压器序列预测体系

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-03-03 DOI: 10.1109/TSM.2026.3669891

Jianming Guo;Kun Ren;Dawei Gao;Dong Ni

{"title":"A Transformer-Based Sequence Prediction Architecture for Etch Profile Evolution in Semiconductor Manufacturing","authors":"Jianming Guo;Kun Ren;Dawei Gao;Dong Ni","doi":"10.1109/TSM.2026.3669891","DOIUrl":"https://doi.org/10.1109/TSM.2026.3669891","url":null,"abstract":"The precise control of three-dimensional feature profiles during plasma etching is a fundamental challenge in nanoscale device fabrication, directly impacting performance and yield. While conventional physics-based simulations can capture the underlying plasma-surface interactions, their prohibitive computational cost limits their use for large-area analysis or rapid process development. To bridge this gap, we introduce EtchFormer, a Transformer-based deep learning framework engineered as a high-speed virtual metrology engine for 3D etch profile prediction. Crucially, the model is trained on a comprehensive dataset generated by the physically-calibrated, multi-scale TCAD simulations described in our methodology. This dataset, comprising over 50,000 time-resolved frames from thousands of etching sequences, embeds the fundamental physics of ion-enhanced etching, surface passivation, and byproduct transport across a wide spectrum of industrial process conditions and complex nanoscale patterns. The EtchFormer framework demonstrates high-fidelity reconstruction of entire etch sequences (Structural Similarity Index >0.945) and, critically, exhibits robust long-range forecasting capabilities by accurately extrapolating profile evolution beyond the temporal range of the training data. Validated on complex layouts, EtchFormer reduces the prediction time for a complete sequence from hours to sub-seconds (~0.3 s). This capability provides a foundation for the virtual metrology, enabling the exploration of complex process-pattern dependencies, the prediction of structural anomalies, and the accelerated design and optimization of etching processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"248-255"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel Structure of a Deep Neural Network-Based Material Removal Rate Prediction Model for Multizone Chemical Mechanical Planarization Process Control 基于深度神经网络的多区化学机械平面化过程控制材料去除率预测模型的新结构

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-03-13 DOI: 10.1109/TSM.2026.3673785

Bangxu Liu;Dewen Zhao;Xinchun Lu;Yuhong Liu

{"title":"Novel Structure of a Deep Neural Network-Based Material Removal Rate Prediction Model for Multizone Chemical Mechanical Planarization Process Control","authors":"Bangxu Liu;Dewen Zhao;Xinchun Lu;Yuhong Liu","doi":"10.1109/TSM.2026.3673785","DOIUrl":"https://doi.org/10.1109/TSM.2026.3673785","url":null,"abstract":"Multizone pressure chemical mechanical planarization (CMP), which is regarded as irreplaceable in semiconductor manufacturing, is highly dependent on a process control strategy. However, predictive models with strict rules for advanced CMP multizone pressure process control have rarely been examined, even with the development of machine learning applications in semiconductor fabrication. Establishing a precise data-driven model that takes the fabrication conditions into consideration is urgent for controlling the CMP process. A novel structure for the CMP material removal rate model consisting of two parts is proposed and validated according to split pressure experiments and feature importance learning by this article. The first part was devoted to the prediction of the polishing time and time dependent problem with a deep neural network. The other part focused on the mutual effect of the pressure distribution on the multizone material removal rate using deep neural network with fully connected layers. To improve the prediction model of the first part, this study devises an advanced predictive model that combines a bidirectional gated recurrent unit network with a multi-head self-attention module and a one-dimensional neural network. This deep network extracts time-varying factors from industrial dataset and establish a nonlinear mapping function from CMP process features to material removal rate with no pressure variables. Both part of this structure is tested and evaluated for the feasibility of the predictive model using dataset from industrial fabrication.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"274-290"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Critical Roles of Copper Surface Planarity in Achieving Reliable Cu/SiO2 Hybrid Bonding 铜表面平面度在实现可靠的Cu/SiO2杂化键合中的关键作用

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-04-02 DOI: 10.1109/TSM.2026.3680409

Kangmin Seo;Sunjae Kim;Junyoung Choi;Suin Jang;Hoogwan Lee;Sarah Eunkyung Kim

{"title":"Critical Roles of Copper Surface Planarity in Achieving Reliable Cu/SiO2 Hybrid Bonding","authors":"Kangmin Seo;Sunjae Kim;Junyoung Choi;Suin Jang;Hoogwan Lee;Sarah Eunkyung Kim","doi":"10.1109/TSM.2026.3680409","DOIUrl":"https://doi.org/10.1109/TSM.2026.3680409","url":null,"abstract":"Fine-pitch interconnects have become essential for high-density 3D integrated circuits, with Cu/SiO<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula> hybrid bonding emerging as a key enabling technology for low-resistance, high-density interconnection. However, Cu pad surface planarity following chemical mechanical polishing (CMP) critically influences bonding quality, with Cu dishing and oxide corner rounding representing a major challenge. This study investigates the relationship between Cu pad dimensions, spacing, and their effects on Cu dishing behavior and hybrid bonding performance. Cu pads with widths of 4, 6, 8, and <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m were designed with varying inter-pad spacings, patterned using standard photolithography, and fabricated through electroplating. CMP was applied, and dishing depths were quantitatively evaluated using atomic force microscopy (AFM). Prior to bonding, two-step Ar/N<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula> plasma surface activation was conducted to remove native oxide and enhance both Cu-Cu and SiO<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula>-SiO<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula> bonding interfaces. <inline-formula> <tex-math>$4~mu $ </tex-math></inline-formula>m pads exhibited minimal dishing and achieved void-free bonding, while 6, 8, and <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>m pads showed progressively deeper dishing and incomplete Cu bonding. In addition to Cu CMP optimization, Cu pad geometry plays a crucial role in determining reliable hybrid bonding quality.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"229-234"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Capacity Planning With Cluster Tool Constraints: Aligning Investment and Input Decisions in Research and Development Semiconductor Fabs 产能规划与集群工具约束：调整投资和投入决策的研究和开发半导体工厂

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-03-26 DOI: 10.1109/TSM.2026.3678007

Jinyoun Lee;Kihong Kim;Seungho Lee;Euiseok Kum

{"title":"Capacity Planning With Cluster Tool Constraints: Aligning Investment and Input Decisions in Research and Development Semiconductor Fabs","authors":"Jinyoun Lee;Kihong Kim;Seungho Lee;Euiseok Kum","doi":"10.1109/TSM.2026.3678007","DOIUrl":"https://doi.org/10.1109/TSM.2026.3678007","url":null,"abstract":"Research and pilot fabrication lines must plan capacity under highly diversified product portfolios, unstable demand, and frequent recipe changes. We present a prescriptive mixed integer linear programming framework that encodes internal mechanisms of cluster tools, including expected clean time after recipe transitions, finite concurrency at load ports and side buffers under a nonmixing policy, and sequential and parallel routing across chambers. The framework supports two planning tasks, minimizing added capacity to relieve bottlenecks and maximizing wafer starts for a given product mix and planning horizon. Using 12 monthly instances from an industrial R&D line, the proposed model improves agreement with the fab reported bottleneck set under substantial mix changes. Relative to a baseline formulation that abstracts cluster tool internals, the bottleneck hit rate increases by 0.0 to 10.5 percentage points across months (average improvement 4.8 percentage points). In addition, the model can screen incremental product releases that do not increase the modeled bottleneck loading, enabling approximately 1.2% additional starts without new equipment.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"291-298"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications 《IEEE电子器件学报：用于射频、功率和光电子应用的超宽带隙半导体器件》特刊征文

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-02-06 DOI: 10.1109/TSM.2026.3657883

引用次数: 0