IEEE Transactions on Semiconductor Manufacturing最新文献_第5页

Sample-Efficient Modeling and Optimization of High-Dimensional Semiconductor Processes Using Output-Augmented Gaussian Process Regression and Dynamic Bayesian Optimization 基于输出增广高斯过程回归和动态贝叶斯优化的高维半导体过程样本高效建模与优化

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-04-14 DOI: 10.1109/TSM.2026.3683804

Om Maheshwari;Nihar R. Mohapatra

{"title":"Sample-Efficient Modeling and Optimization of High-Dimensional Semiconductor Processes Using Output-Augmented Gaussian Process Regression and Dynamic Bayesian Optimization","authors":"Om Maheshwari;Nihar R. Mohapatra","doi":"10.1109/TSM.2026.3683804","DOIUrl":"https://doi.org/10.1109/TSM.2026.3683804","url":null,"abstract":"Semiconductor process modeling in early stages of process development is challenging due to limited availability of the data, high dimensionality of inputs and outputs, and chamber-to-chamber (C2C) variations. This paper presents a unified ‘OGE’ framework combining Output Augmented Modeling (OAM) to Gaussian Process Regression (GPR), with Ensemble Feature Removal (EFR) to address these issues. EFR robustly eliminates weak predictors across multiple validation trials, while OAM recursively enhances model accuracy by incorporating high-performing outputs as auxiliary inputs. The resulting multi-input single-output models are stitched into a multi-output structure and optimized using Dynamic Bayesian Optimization to meet target specifications. Applied to four semiconductor process datasets with up to 100 input features and fewer than 85 samples, the proposed approach consistently outperforms conventional techniques, demonstrating improved generalization, interpretability, and robustness to C2C variations. The framework provides actionable insights for process tuning and is well-suited for data-driven optimization in early-stage semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"266-273"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Best Paper Award 2025 最佳论文奖2025

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-03-15 DOI: 10.1109/TSM.2026.3685866

Jun Haeng Lee;Soichi Inoue;Gian Antonio Susto;Shubhodeep Goswami;Mahadeva Iyer Natarajan;Reha Uzsoy

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Finite Element Simulation of Localized Flip-Chip Thermo-Compression Bonding for GaN-Based Micro-LEDs 基于gan的微型led局部倒装芯片热压缩键合的有限元模拟

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-06 DOI: 10.1109/TSM.2026.3661882

Zhihua Wang;Kaixin Zhang;Qun Yan;Chang Lin;Xiongtu Zhou;Jie Sun

{"title":"Finite Element Simulation of Localized Flip-Chip Thermo-Compression Bonding for GaN-Based Micro-LEDs","authors":"Zhihua Wang;Kaixin Zhang;Qun Yan;Chang Lin;Xiongtu Zhou;Jie Sun","doi":"10.1109/TSM.2026.3661882","DOIUrl":"https://doi.org/10.1109/TSM.2026.3661882","url":null,"abstract":"Micro light-emitting diode (Micro-LED) has attracted significant research interest owing to its outstanding optoelectronic properties. Flip-chip thermo-compression bonding is a critical step in its manufacturing process, wherein a systematic investigation of process parameters is essential for ensuring bonding quality. Conventional process development heavily relies on experimental trial-and-error approaches, which are time-consuming and costly, thus necessitating the integration of simulation technologies for efficient optimization. Existing simulation studies predominantly focus on single-pixel device bonding; however, this approach faces practical challenges such as high-precision alignment requirements, mechanical damage, particle contamination, and positional inaccuracies introduced during mass transfer. In contrast, directly bonding an unpatterned, full Micro-LED epitaxial wafer to a driver substrate, followed by pixel definition through photolithography and etching, circumvents the mass transfer procedure, thereby enhancing process yield and robustness. Nevertheless, simulation research on this direct bonding strategy remains scarce. To address this gap, this paper develops a localized representative finite element model to simulate the thermo-compression bonding process between a Micro-LED epitaxial chip and a driver substrate incorporating a representative <inline-formula> <tex-math>$10times 10$ </tex-math></inline-formula> Au bump array. The study focuses on the thermomechanical coupling behavior within the bump array, with systematic analysis of the influences exerted by structural dimensions, bump geometry, and temperature on stress and deformation distributions. To alleviate the issue of stress concentration at the array periphery, a mitigation approach using stress buffer layers filled between bumps is proposed. Results show that adopting polyimide as a buffer layer markedly improves stress distribution uniformity, thereby reducing potential failure risks.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"184-189"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148506637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Transactions on Semiconductor Manufacturing Publication Information IEEE半导体制造学报

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-03-15 DOI: 10.1109/TSM.2026.3673808

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Evaluating the Impact of Emerging Contaminants on Membrane Performance in Ultrapure-Water Production for Semiconductor Manufacturing: A PRISMA-Directed Meta-Analysis 评估半导体制造中超纯水生产中新兴污染物对膜性能的影响：棱镜导向的meta分析

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-01-23 DOI: 10.1109/TSM.2026.3657662

Hafiz Usama Tanveer;Hasham Tanveer;Sheeza Fatima;Rai Faisal Aslam;Hamza Tanveer;Muhammad Hashier Muneeb Farrukh

{"title":"Evaluating the Impact of Emerging Contaminants on Membrane Performance in Ultrapure-Water Production for Semiconductor Manufacturing: A PRISMA-Directed Meta-Analysis","authors":"Hafiz Usama Tanveer;Hasham Tanveer;Sheeza Fatima;Rai Faisal Aslam;Hamza Tanveer;Muhammad Hashier Muneeb Farrukh","doi":"10.1109/TSM.2026.3657662","DOIUrl":"https://doi.org/10.1109/TSM.2026.3657662","url":null,"abstract":"Ultrapure water (UPW) is indispensable in semiconductor manufacturing, where it serves as the foundational input for wafer cleaning, chemical dilution, and rinsing steps. As device geometries shrink below 5 nm, even parts-per-trillion (ppt) levels of contaminants can compromise yield, reliability, and compliance with industry standards such as SEMI F63 and ASTM D5127. Emerging contaminants (ECs) including per- and polyfluoroalkyl substances (PFAS), pharmaceuticals and personal care products (PPCPs), chemical mechanical planarization (CMP) organics, and micro/nanoplastics pose new challenges for membrane-based UPW treatment systems, especially under evolving regulations like the EPA PFAS Rule (2024). This PRISMA-guided meta-analysis evaluates 31 peer-reviewed studies (2002–2025) to quantify how reverse osmosis (RO), nanofiltration (NF), and ultrafiltration (UF) membranes perform under EC exposure. RO consistently achieved >99% rejection for long-chain PFAS and PPCPs but showed lower efficacy (93.8–99.2%) for short-chain compounds. NF demonstrated variable rejection (86–98%) depending on compound characteristics but offered energy savings in suitable contexts. UF was effective for microplastics but suffered significant flux decline (15–45%) with CMP-related organics. These findings offer critical, data-driven insights for semiconductor facilities seeking to maintain compliance, reduce operating costs, and optimize yield amid stricter water quality demands.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"358-368"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Fast Global Sparse Principal Component Analysis for Sensor Reduction in Virtual Metrology 虚拟计量中传感器约简的快速全局稀疏主成分分析

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-01-28 DOI: 10.1109/TSM.2026.3658988

Yifan Xie;Tianhui Wang;Myong K. Jeong

{"title":"Fast Global Sparse Principal Component Analysis for Sensor Reduction in Virtual Metrology","authors":"Yifan Xie;Tianhui Wang;Myong K. Jeong","doi":"10.1109/TSM.2026.3658988","DOIUrl":"https://doi.org/10.1109/TSM.2026.3658988","url":null,"abstract":"In semiconductor manufacturing, virtual metrology (VM) leverages high-dimensional sensor data for real-time quality estimation. However, excessive sensor deployment leads to increased operational costs, data redundancy, and system complexity due to substantial infrastructure, installation, and maintenance requirements. To address these manufacturing challenges, we propose a Fast Global Sparse Principal Component Analysis (FGS-PCA) framework for systematic sensor reduction in VM applications. FGS-PCA efficiently constructs sparse principal components that capture dominant variance while strictly enforcing a global constraint on the total number of sensors used across components, a critical requirement for cost-effective industrial deployment. Unlike existing sparse PCA methods that impose sparsity on each principal component independently, FGS-PCA explicitly controls the total sensor count across all components, enabling structured dimensionality reduction aligned with real-world manufacturing constraints. The framework combines a computationally efficient sparse loading identification approach with an optional anchor-based refinement step to achieve near-optimal variance retention while significantly reducing sensor requirements. The proposed method offers a scalable, interpretable, and practically deployable solution that enables substantial cost savings while maintaining process control effectiveness in modern semiconductor manufacturing systems.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"235-247"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148504427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Automating Root Cause Analysis in Semiconductor Manufacturing Using Transformer Models With Explainable AI 利用变压器模型和可解释的人工智能自动化半导体制造中的根本原因分析

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-04-07 DOI: 10.1109/TSM.2026.3681810

Youssef Alothman;Mohamed Bader-El-Den;Lalit Maurya;Eslam Amer

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LSTM-Based Automated Analysis of Laser-Groove Profiles in Wafer Dicing Using White-Light Interferometry Data 基于lstm的白光干涉数据自动分析晶圆切割激光沟槽轮廓

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-16 DOI: 10.1109/TSM.2026.3665338

I-Ching Lu;Hsin-Hung Chou;Shih-Ching Yeh;Eric Hsiao-Kuang Wu

{"title":"LSTM-Based Automated Analysis of Laser-Groove Profiles in Wafer Dicing Using White-Light Interferometry Data","authors":"I-Ching Lu;Hsin-Hung Chou;Shih-Ching Yeh;Eric Hsiao-Kuang Wu","doi":"10.1109/TSM.2026.3665338","DOIUrl":"https://doi.org/10.1109/TSM.2026.3665338","url":null,"abstract":"Laser grooving is a critical preparatory step in wafer dicing for advanced semiconductor packaging, ensuring reduced mechanical stress and improved dicing precision. However, groove quality assessment remains challenging due to profile irregularities and noise in depth measurement data. This paper presents an automated groove inspection system that leverages long short-term memory (LSTM) networks to analyze depth profiling data acquired via white light interferometry. The proposed method predicts the original wafer surface level and extracts key groove metrics, including groove depth, width, and debris zone characteristics. Unlike traditional rule-based or image-based methods, the LSTM-based model processes 1D cross-sectional height profiles directly, achieving a prediction accuracy of 99.87% under practical industrial tolerances. The system integrates seamlessly into semiconductor manufacturing pipelines, supporting real-time process monitoring, adaptive parameter tuning, and predictive maintenance. Experimental results validate the superiority of the proposed approach over conventional techniques, offering enhanced robustness, accuracy, and scalability for high-throughput wafer-level metrology.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"175-183"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Advanced SHG Metrology for Epitaxial SiGe Characterization in Semiconductor Manufacturing 半导体制造中外延SiGe表征的先进SHG计量

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-02-09 DOI: 10.1109/TSM.2026.3662500

Zhongming Liu;Jintai Liang;Puxi Zhou;Guangwei Xu;Shibing Long

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Comprehensive Framework for Identifying and Visualizing Key Yield Factors in Semiconductor Manufacturing 半导体制造中关键良率因素识别和可视化的综合框架

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2026-03-01 Epub Date: 2026-03-11 DOI: 10.1109/TSM.2026.3673232

Gyeunggeun Doh;Jeongwoo Seo;Sanghoun Oh;Minseok Song

{"title":"Comprehensive Framework for Identifying and Visualizing Key Yield Factors in Semiconductor Manufacturing","authors":"Gyeunggeun Doh;Jeongwoo Seo;Sanghoun Oh;Minseok Song","doi":"10.1109/TSM.2026.3673232","DOIUrl":"https://doi.org/10.1109/TSM.2026.3673232","url":null,"abstract":"Semiconductor manufacturing involves complex multistage processes in which product yield is influenced by intricate interactions among machines, materials, recipes, process durations, queue times, and wafer characteristics, such as warpage. Traditional yield analysis methods typically examine these factors in isolation, overlooking their combined effects. To address this limitation, we propose a novel framework based on Transition System (TS) modeling that jointly analyzes high-dimensional process attributes to improve yield understanding and prediction. The framework achieves three goals: 1) quantifying the impact of individual process attributes on yield; 2) identifying interacting attribute combinations that produce best-of-best (BOB) and worst-of-worst (WOW) wafer paths; and 3) visualizing these patterns through an interpretable TS model. We first encode each wafer’s event log as a sequence of discrete state attributes - machine, material, recipe, queue time, duration, and warpage - and then construct a TS model that connects adjacent states. Critical attributes are selected through random forest feature importance, followed by association rule mining to extract yield-relevant state combinations. The final model enables classification of wafers into high- or low-yield categories and provides visual insight into the process behavior. Experiments using real production data from a Korean semiconductor facility demonstrate the effectiveness of the framework in uncovering key yield drivers and supporting data-driven process optimization.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 2","pages":"190-199"},"PeriodicalIF":2.5,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11430710","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148505077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0