IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TSM.2025.3595469","DOIUrl":"https://doi.org/10.1109/TSM.2025.3595469","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"734-735"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132358","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TSM.2025.3595473","DOIUrl":"https://doi.org/10.1109/TSM.2025.3595473","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"738-739"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132377","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editorial Special Section on the 2024 SEMI Advanced Semiconductor Manufacturing Conference","authors":"Jeanne Paulette Bickford;Delphine Le Cunff;Ralf Buengener;Stefan Radloff;Paul Werbaneth","doi":"10.1109/TSM.2025.3594797","DOIUrl":"https://doi.org/10.1109/TSM.2025.3594797","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"372-374"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132375","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2025.3595357","DOIUrl":"https://doi.org/10.1109/TSM.2025.3595357","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132376","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TSM.2025.3575487","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575487","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"736-737"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132379","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Semiconductor Manufacturing Publication Information","authors":"","doi":"10.1109/TSM.2025.3595355","DOIUrl":"https://doi.org/10.1109/TSM.2025.3595355","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"C2-C2"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132374","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"In-House Test Wafer Reclaim for Fab Cost and Wastage Reduction","authors":"Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie","doi":"10.1109/TSM.2025.3594906","DOIUrl":"https://doi.org/10.1109/TSM.2025.3594906","url":null,"abstract":"In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. These insights are intended for dissemination as an innovative method to achieve hundreds of millions of dollars annualized network savings and significant wastage reduction.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"391-398"},"PeriodicalIF":2.3,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Autonomous Robot Orchestration Solution for OHT With Active Q Routing and Digital Twin FA: Factory Automation","authors":"Jaeho Lee;Jinhyeok Park;Sangpyo Hong;Illhoe Hwang;Seol Hwang;Young Jae Jang;Donghwi Shin;Jaeung Lee","doi":"10.1109/TSM.2025.3594651","DOIUrl":"https://doi.org/10.1109/TSM.2025.3594651","url":null,"abstract":"The Autonomous Robot Orchestration Solution (AROS) is transforming the management of robot fleets by identifying the state and environment of each robot and enabling them to collaborate toward common goals. This paper introduces AROS and its application in controlling massive fleets of Overhead Hoist Transport (OHT) vehicles in semiconductor fabrication facilities. AROS leverages key technologies, including reinforcement learning algorithms, discrete event simulation, and real-time data collection through Digital Twin (DT). The DT replicates the real system in a virtual environment with real-time communication to optimize decision-making for OHTs. A key innovation of AROS is the introduction of active Q routing, a dynamic routing method that adapts to changing traffic conditions by predicting and adjusting travel times through discrete event simulation. Active Q routing enhances operational efficiency by mitigating congestion and reducing delays, even in highly dynamic environments. We demonstrate the effectiveness of AROS and active Q routing on OHT system performance, showcasing reductions in average delivery times and increases in delivery capacity. These findings are validated through real-world use cases in a large-scale semiconductor fab.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"404-412"},"PeriodicalIF":2.3,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving Endpoint Detection Sensitivity in Plasma Etching With Small Openings","authors":"Lianhao Qi;Jingyuan Mao;Xiaoyang Chang;Xiaoyang Lin;Xinhe Wang","doi":"10.1109/TSM.2025.3588602","DOIUrl":"https://doi.org/10.1109/TSM.2025.3588602","url":null,"abstract":"We propose a method that enables real-time endpoint detection during plasma etching of small openings (the absolute area of the opening is at or below 5%) on a wafer. Traditional endpoint detection techniques rely on observing changes in specific wavelengths, which perform well for wafers with larger openings. However, as integrated circuit manufacturing processes continue to develop towards miniaturization, real-time endpoint detection in small opening areas remains a significant challenge. This method utilizes strategies such as hybrid noise reduction, dimensionality reduction, and interpolation to achieve real-time monitoring of etching status. First of all, a spectrometer is used to monitor chamber status in real time and provide spectral data. The wavelet threshold combined with median filtering was used to denoise the data, the SNR of the spectral signal processed by the mixed strategy increases by 37.87% compared to that of the noisy signal. What’s more, 86.96% dimensionality reduction can be achieved through the spectral data dimensionality reduction rule. Finally, an offline model was constructed using a three-time spline interpolation for the selected feature wavelengths. Compared with other strategies, the sensitivity of endpoint detection in small opening areas of the model constructed by the above algorithm is increased by 13.2%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"717-727"},"PeriodicalIF":2.3,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Innovative Design of a Compensation Structure for Anisotropic Etching of Adjacent Convex Corners","authors":"Yuxiang Xu;Yihui Xu;Zhichao Zhang;Jianqiang Han","doi":"10.1109/TSM.2025.3589216","DOIUrl":"https://doi.org/10.1109/TSM.2025.3589216","url":null,"abstract":"While deeply etching silicon to form various microstructures with bosses or crossing splitting grooves with a V-shaped or trapezoidal cross section, the etching solution will undercut convex corners. The major problem associated with compensation structure design is the large spatial requirement around the convex corners. This paper proposes a compensation pattern to compensate the undercutting of adjacent convex corners of crossing splitting grooves. Four square masks are set at the convex corners of each chip. The twelve convex corners of four square masks are connected by six <110> oriented clamped-clamped beams. In the first stage of etching, the etching solution undercuts <110> oriented clamped-clamped beams from both sides instead of from both ends. The lateral undercutting rate of the narrow clamped-clamped beams is only 9.6% of the etching rate of the (100) plane in 80°C 25% TMAH solution. This greatly reducing the size of compensation pattern between four adjacent convex corners. Square masks are used to protect the convex corners of each chip from being etched during maskless etching the silicon wedges under clamped-clamped beams. This convex corner compensation pattern reduces the width of splitting grooves and improves the yield.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"687-692"},"PeriodicalIF":2.3,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}