内部测试晶圆回收,以降低晶圆厂成本和浪费

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie
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引用次数: 0

摘要

在半导体制造设施中,非生产测试晶圆构成了非设备相关消耗品费用的很大一部分。随着裸硅测试晶圆需求的不断增长和成本的增加,以及外部回收可行性的有限,对于主要芯片制造商来说,延长回收晶圆的生命周期和建立内部回收工艺的必要性已经变得明显。外部回收通常伴随着更高的成本和有限的回收寿命。相比之下,内部回收的成本要低得多,每片晶圆的外部回收成本只有一小部分,并且回收寿命更长,使其成为更具成本效益的解决方案。从历史上看,半导体晶圆厂缺乏修复已达到使用寿命的测试晶圆的能力。不符合全球规格的测试晶圆被降级并外包给外部供应商进行回收。本文提出了一种创新的方法,结合了无定形二氧化硅细浆、半硬垫配置和优化的擦洗清洗,与外部回收相比,成本降低了93%,回收寿命延长了三倍。美光最近开发的内部晶圆回收工艺具有显着的收率提高,符合全球回收规范。此外,一种新型CMP(化学机械抛光)浆料的新组合以及CMP和湿法工艺的工艺优化已被设计并有效地应用于回收工艺,在大批量操作中实现了令人印象深刻的回收收率。这些进步为半导体制造中的内部回收和回收过程注入了信心。虽然具体数字仍然保密,但本文的结果强调了内部硅片回收的可行性,并阐明了一种具有成本效益的高产量方法。这些见解旨在作为一种创新方法进行传播,以实现每年数亿美元的网络节省和显著的浪费减少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
In-House Test Wafer Reclaim for Fab Cost and Wastage Reduction
In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. These insights are intended for dissemination as an innovative method to achieve hundreds of millions of dollars annualized network savings and significant wastage reduction.
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来源期刊
IEEE Transactions on Semiconductor Manufacturing
IEEE Transactions on Semiconductor Manufacturing 工程技术-工程:电子与电气
CiteScore
5.20
自引率
11.10%
发文量
101
审稿时长
3.3 months
期刊介绍: The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.
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