Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie
{"title":"内部测试晶圆回收,以降低晶圆厂成本和浪费","authors":"Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie","doi":"10.1109/TSM.2025.3594906","DOIUrl":null,"url":null,"abstract":"In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. These insights are intended for dissemination as an innovative method to achieve hundreds of millions of dollars annualized network savings and significant wastage reduction.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"391-398"},"PeriodicalIF":2.3000,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"In-House Test Wafer Reclaim for Fab Cost and Wastage Reduction\",\"authors\":\"Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie\",\"doi\":\"10.1109/TSM.2025.3594906\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. 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In-House Test Wafer Reclaim for Fab Cost and Wastage Reduction
In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. These insights are intended for dissemination as an innovative method to achieve hundreds of millions of dollars annualized network savings and significant wastage reduction.
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.