IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"Optimizing Polysilicon Resistor Fabrication via BF2 + F Co-Implantation: A Manufacturing-Compatible Approach for Low Resistance and High Reliability in MOS Devices","authors":"Lee Sai Link;Mohamed Fauzi Packeer Mohamed;Tan Chan Lik","doi":"10.1109/TSM.2025.3587715","DOIUrl":"https://doi.org/10.1109/TSM.2025.3587715","url":null,"abstract":"This study investigates the impact of BF<inline-formula> <tex-math>${}_{2} {+}$ </tex-math></inline-formula> F co-implantation at various energies on the electrical and structural characteristics of Polysilicon resistors in MOS devices. The introduction of Fluorine effectively reduces the Polysilicon sheet resistance by 10.13% while also optimizing the Temperature Coefficient of Resistance (TCR) at higher energy implantation. A grain-boundary passivation model is used to explain the reduction in sheet resistance caused by the addition of Fluorine. This is supported by evidence of grain size enhancement and surface roughness reduction, attributed to an increased concentration of Si-F bonds as observed through FTIR analysis. Furthermore, the incorporation of Fluorine results in a decrease in Gate capacitance and an increase in Gate breakdown voltage. A novel mechanism is proposed to explain the impact of Fluorine on Gate capacitance by the formation of a low-k SiOF layer. Additionally, higher Fluorine implantation energy improves the reliability of Polysilicon resistors by mitigating sheet resistance drift under constant 40 V electrical and thermal stress at various temperatures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"709-716"},"PeriodicalIF":2.3,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Semisupervised Lithography Hotspot Detection Model Based on Dual-Branch Auxiliary Classification","authors":"Hui Xu;Wenxin Huang;Xinzhong Xiao;Ye Yuan;Ruijun Ma;Fuxin Tang;Pan Qi;Huaguo Liang","doi":"10.1109/TSM.2025.3586456","DOIUrl":"https://doi.org/10.1109/TSM.2025.3586456","url":null,"abstract":"Due to the low accuracy and high false alarm rate of conventional semisupervised lithography hotspot detection models, we propose a semisupervised hotspot detection model based on dual-branch auxiliary classification comprising a classification stream, a dual-branch auxiliary classification stream, and a clustering stream. The classification stream assigns labels to input samples. The auxiliary classification stream consisting of two branches validates the classification results. Moreover, the clustering stream estimates the confidence of the sample labels. Due to the imbalance of the dataset, the model integrates a random data augmentation method to increase the hotspot samples and thus enhance model performance. Additionally, false positive rate (FPR) is used to assess model performance across all benchmarks in the ICCAD 2012 dataset. The experimental results demonstrate that our model achieves higher accuracy and a lower FPR while requiring less overall detection and simulation time across different proportions of labeled samples compared with the state-of-the-art model.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"522-532"},"PeriodicalIF":2.3,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"BDSD-Net: An Efficient and High-Precision Anomaly Detector for Real-Time Semiconductor Wafer Vision Inspection","authors":"Shuang Mei;Zhaolei Diao;Xingyue Liu;Guojun Wen","doi":"10.1109/TSM.2025.3585570","DOIUrl":"https://doi.org/10.1109/TSM.2025.3585570","url":null,"abstract":"The advancement of integrated circuit fabrication processes has resulted in a concomitant increase in the complexity and frequency of surface defects on semiconductor wafers. This underscores the necessity for precise, real-time quality monitoring and control to enhance yield, cost-efficiency, and performance. Traditional automatic optical inspection (AOI) methods based on die-to-golden sample, die-to-die, or general deep learning-based semantic segmentation models often fail to meet these requirements due to insufficient detection accuracy, high false alarm rates, or inadequate throughput. To address these challenges, this paper proposes BDSD-Net, an efficient real-time detector that achieves state-of-the-art (SoTA) performance in wafer surface defect detection. Initially, a novel lightweight MVHNet backbone is developed, which seamlessly integrates the synergistic strengths of convolutional neural networks (CNNs) and Transformers within a ResNet-inspired architecture. Subsequently, an adaptive hybrid encoder is engineered to reduce the interference caused by intricate background patterns, thereby enhancing the accuracy of defect segmentation. This encoder includes an adaptive intra-scale feature interaction (ADFI) module that extracts more detailed high-level semantic information, and an adaptive multi-scale feature fusion (AMFF) module that effectively merges defect features across various scales. Moving away from high-complexity encoder structures, an efficient multi-scale residual fusion (EMRF) module is developed to narrow down the hypothesis space, thereby accelerating convergence. Finally, a knowledge distillation training strategy is also implemented to equip the lightweight model with the learning capabilities of more complex network models, thus enhancing its mean average precision (mAP) and frames per second (FPS) in inspection tasks. Extensive experimental results demonstrate the effectiveness of our method with data volume robustness, which achieves 88.2% and 88.9% mAP@0.5 on the semiconductor wafer and chip datasets. Moreover, compared to SoTA methods, our framework shows superior performance, achieving a compact model size of only 27 MB and a detection speed of 108.4 FPS. The demo code of this work is publicly available at <uri>https://github.com/Adiao2001/BDSD-Net/</uri>.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"675-686"},"PeriodicalIF":2.3,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reduced Topography After Stop on Nitride (SON) STI CMP Through Improved Post-Bulk Planarity for Diverse Layouts in Advanced Nodes","authors":"Max Constantin Klotzsche;Shubhada Sunil Shetti;Benjamin Lilienthal-Uhlig;Conrad Guhl","doi":"10.1109/TSM.2025.3584390","DOIUrl":"https://doi.org/10.1109/TSM.2025.3584390","url":null,"abstract":"Three methods for improving planarization in a ceria free, two step STI CMP process were investigated using patterned test wafers representing 2X nm technology. It was found that within die non-uniformity (WIDNU) after bulk CMP can be improved with (1) higher oxide overburden, (2) reduced bulk polish pressure and (3) intermittent polishing by up to 15, 30 and 41% respectively. Intermittent polishing consists of alternating polish and water rinse intervals with continuous conditioning. By combining these methods up to 33% lower WIDNU is achieved post-SON, while oxide dishing for large open areas on the scale of 0.1 and 1 mm is reduced by up to 43% and 46% respectively. All three methods only require minor process changes and may help silica slurry to replace common ceria slurry in certain applications where price, particle contamination, sustainability and supply risk are the deciding factors.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"659-666"},"PeriodicalIF":2.3,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11063224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of Thick Silicon Nitride Film Properties at 300 mm Scale for High-Q Photonic Devices","authors":"Soumen Kar;Nicholas W. Gangi;Katrina A. Morgan;Lewis G. Carpenter;Nicholas M. Fahrenkopf;Yukta Timalsina;Christopher V. Baiocco;David Harame","doi":"10.1109/TSM.2025.3583925","DOIUrl":"https://doi.org/10.1109/TSM.2025.3583925","url":null,"abstract":"This work evaluates thick silicon nitride (SiN) film properties using various inline and offline advanced metrology data analysis. The thick SiN films for photonic applications are typically prepared by plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD) techniques. Our present study combines high-volume inline and high-accuracy offline metrology to best characterize our thick SiN films. The developed SiN film compositional analysis has been carried out using inline X-ray photoelectron spectroscopy (XPS) to get fast feedback on the composition and contamination of the film surface. Finally, we present a refractive index (n) comparison for annealed and unannealed PECVD/LPCVD wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"420-427"},"PeriodicalIF":2.3,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process-Aware Digital Twins by Deep Learning for DUV Photolithography and Plasma Etch","authors":"Christina L. Lau;Shuhan Ding;Yutong Xie;Edwin R. Law;Bahar Kor;Benyamin Davaji;Amit Lal;Peter C. Doerschuk","doi":"10.1109/TSM.2025.3582194","DOIUrl":"https://doi.org/10.1109/TSM.2025.3582194","url":null,"abstract":"Computer representations of the structure, context, and behavior of physical systems are critical components of computational system optimization. Traditionally, such optimization is done by iterative physical experiments, which can be expensive both in time and resources. In this paper, these computer representations, called digital twins, are developed primarily using SEM images and equipment process parameters. HyperPix2Pix, the proposed methodology of the digital twins, is a deep neural network that uses SEM images of the input structure together with equipment process parameters to predict the output SEM images. We demonstrate HyperPix2Pix on a DUV photolithography stepper and plasma etcher. HyperPix2Pix predicts output images that closely match the experimental output images and have very similar critical dimensions. Compared to previous work, HyperPix2Pix includes the effects of process parameters through multimodal learning, elucidating the role of different parameters in nanofabrication processes and their effects on critical dimensions of the resulting structures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"634-641"},"PeriodicalIF":2.3,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automated Construction of Semi-Physical CMP Models via Embedded Neural Networks","authors":"Qian Yue;Chen Lan","doi":"10.1109/TSM.2025.3581909","DOIUrl":"https://doi.org/10.1109/TSM.2025.3581909","url":null,"abstract":"The planarization of chip surfaces after chemical mechanical planarization (CMP) is becoming increasingly crucial as it can lead to problems such as depth of focus (DOF), voltage drop (IR drop), timing closure and electromigration (EM) problems. To enhance production yield, the industry requires an accurate CMP model to detect, localize, and control topography nonuniformity caused by layout dependent effects (LDE) prior to fabrication. However, existing semi-physical models heavily rely on manually specified empirical relationships during the calibration process, limiting their ability to meet the demands of advanced process nodes in terms of automated model construction and prediction accuracy. To address this limitation, we propose to construct empirical relationships in semi-physical models using embedded neural networks. Building upon this concept, we have developed a deep-learning-assisted semi-physical CMP model that eliminates the need for manual specification of empirical relationships. Experimentation conducted on silicon data from test chips across the process nodes of 28/32/40 nm highlights the advantages of our model, including rapid training (requiring fewer than 400 epochs), automated deployment and competitive prediction accuracy compared to data-driven models (RMSE reduction for dishing (18%/79%/55%) and erosion (25%/58%/61%) over traditional semi-physical models).","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"533-542"},"PeriodicalIF":2.3,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Avalanche Capability Improvement by Optimizing p+ Contact Resistance for N-Channel Trench Power MOSFETs","authors":"Keisuke Miyamoto;Daichi Ishi;Hiroyuki Kishimoto;Kazuyuki Sato;Tsuyoshi Kachi;Hiroaki Kato","doi":"10.1109/TSM.2025.3581170","DOIUrl":"https://doi.org/10.1109/TSM.2025.3581170","url":null,"abstract":"In the process of Nch silicon MOSFET, BPSG is generally used as an interlayer film. BPSG has the purpose of gettering mobile ions and reflowing the BPSG film by annealing to reduce the steps on the wafer surface. This annealing process also activates the p+ diffusion layer. However, because the annealing temperature at which BPSG is reflowed is high, phosphorus oxide diffuses outward from the BPSG film and penetrates into the contact part. If the contact resistance increases, a serious problem occurs in which the avalanche capability decreases. We have devised two countermeasures to this problem and verified them through experiments. By changing the annealing conditions and increasing the titanium thickness, we were able to reduce the p+ contact resistance by 3 to 4 orders of magnitude and confirmed an improvement in avalanche capability. These countermeasures can be used universally by adjusting them even if the annealing condition changes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"453-458"},"PeriodicalIF":2.3,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effective Deep Reinforcement Learning for Dynamic Machine Allocation: A Case Study on Metal Sputtering Tools","authors":"Hsin-Tzu Hsu;Shi-Chung Chang","doi":"10.1109/TSM.2025.3579970","DOIUrl":"https://doi.org/10.1109/TSM.2025.3579970","url":null,"abstract":"Dynamic Machine Allocation (DMA) is a vital aspect of production scheduling in semiconductor manufacturing. Current DMA practices heavily rely on engineers’ domain expertise and require a few days of manual adjustments in response to rapid but significant fab changes, for example, due to unfamiliar economic shifts. Slow and heuristic DMA policy adaptation very often leads to production shortfalls. To reduce dependence on human expertise and speed up quality responses to changes, we design a framework of effective deep reinforcement learning (DRL) for DMA. Design innovations of the framework include (1) a discrete-event simulator for predicting production flows among machines with state, DMA action and reward aligned to fab practices; (2) a DRL neural network output transformation module that ensures action feasibility in task compatibility and machine availability; and (3) a DRL-based, two-stage agent of DMA policy learning that integrates DRL with optimization techniques for both efficient computation and quality DMA. Operation simulation by using the DMA case and data of a metal sputtering machine group demonstrates that our DRL-based design effectively learns DMA policies in different scenarios, each within one hour. In throughput performance, learned policies surpass a traditional heuristic by 3% to 20%. Our framework and the DRL-based method designs are generic and applicable to DMA of various machine groups.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"430-438"},"PeriodicalIF":2.3,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Modeling of Post-Annealing and Etching Processes of ALD SiO₂ Using Intermediate Variables Considering Digital Twin Model Reusability","authors":"Ryosuke Okachi;Masanori Usui;Tomohiko Mori;Junya Muramatsu;Makoto Kuwahara;Daigo Kikuta","doi":"10.1109/TSM.2025.3579474","DOIUrl":"https://doi.org/10.1109/TSM.2025.3579474","url":null,"abstract":"In this study, we examined a digital twin model that has multiple processes. Generally, previous processes affect subsequent processes in the semiconductor manufacturing process. Therefore, to construct reusable modular models, the mutual influences between processes should be defined and concisely represented. We built a digital twin model involving the post-annealing and wet etching of an oxide film formed by atomic layer deposition (ALD), as a case study. We developed a modular model that separated processes based on intermediate variables extracted through physical analysis. The high coefficient of determination obtained from the prediction results suggests that these intermediate variables sufficiently captured the effect of the preceding processes. Further, we explored concepts for improving model reusability using class structure analysis within an object-oriented programming (OOP) framework. We observed the need for encapsulating physics-based intermediate variables within appropriate classes to separate process- and device-specific descriptions. The encapsulated intermediate variables indirectly represented process influence and enabled the modularization of class-internal models. These findings help in reducing dependencies between models, thereby contributing to improved model reusability.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"487-491"},"PeriodicalIF":2.3,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}