IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"Improving Doping Efficiency of Mist-CVD Epitaxy for Tin-Doped α-Ga₂O₃ Using Tin Chloride Pentahydrate","authors":"Han-Yin Liu;Yun-Yun Cheng;Wei-Han Chen;Ko-Fan Hu;Nei-En Chiu","doi":"10.1109/TSM.2024.3475730","DOIUrl":"https://doi.org/10.1109/TSM.2024.3475730","url":null,"abstract":"Tin chloride pentahydrate (SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O) is used as the dopant precursor to form the n-type \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3 in this study. The X-ray diffraction (XRD) and high-resolution transmission electron microscope (HR-TEM) confirm that the single-crystalline \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O epi-layer was grown on the r-plane sapphire substrate using mist chemical vapor deposition (mist-CVD). When the Sn doping atomic concentrations are the same, the electron concentration of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O is higher than that of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{2}}} cdot 2$ </tex-math></inline-formula>\u0000 H2O. The lower thermal decomposition temperature and lower residues of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O are confirmed in thermogravimetric (TGA) analysis. Sn \u0000<inline-formula> <tex-math>$3d_{5/2}$ </tex-math></inline-formula>\u0000 binding energy spectra observed by X-ray photoelectron spectroscopy (XPS) show that SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O provides more \u0000<inline-formula> <tex-math>$Sn^{4+}$ </tex-math></inline-formula>\u0000 than SnCl\u0000<inline-formula> <tex-math>${_{{2}}} cdot 2$ </tex-math></inline-formula>\u0000 H2O. The specific contact resistivity of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O reaches \u0000<inline-formula> <tex-math>$1.62times 10{^{-}5 }~Omega $ </tex-math></inline-formula>\u0000-cm2 with \u0000<inline-formula> <tex-math>$10^{20}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-}3 $ </tex-math></inline-formula>\u0000 Sn doping concentration. Moreover, the power figure-of-merit (PFoM) of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O-based lateral Schottky barrier diode (SBD) is 0.356 GW/cm2 which is comparable to \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3-based SBD.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"629-633"},"PeriodicalIF":2.3,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantitative 3-D Flow Visualization of Conventional Purge Flow Within a Front Opening Unified Pod (FOUP)","authors":"Sung-Gwang Lee;Juhan Bae;Hoomi Choi;Jaein Jeong;Youngjeong Kim;Wontae Hwang","doi":"10.1109/TSM.2024.3473868","DOIUrl":"https://doi.org/10.1109/TSM.2024.3473868","url":null,"abstract":"The front opening unified pod (FOUP) is a carrier that transports multiple wafers as it moves between numerous processing facilities. It is inevitably exposed to air humidity coming from the equipment front end module (EFEM), which leads to the formation of harmful residual particles on the wafer surfaces due to the reaction of moisture with airborne molecular contamination (AMC). This can cause serious defects, and thus there is a need to understand the complex flow structure inside the EFEM and FOUP. Magnetic resonance velocimetry (MRV) is hereby employed to qualitatively and quantitatively measure the 3D flow when conventional load port purge (LPP) is utilized to protect the wafers. The front LPP forms a barrier between the FOUP and EFEM, blocking the EFEM flow from entering the FOUP. Additionally, at the rear of the FOUP, flow from the rear and front LPP collide and then travels between the wafers toward the FOUP entrance, thereby protecting the wafers. Using computational fluid dynamic (CFD) simulations, various combinations of flow rates from different purge ports were simulated, leading to an optimal flow condition. These findings suggest that independent control of the flow rates can be a practical way to protect the wafers from defects.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"620-628"},"PeriodicalIF":2.3,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Knowledge Distillation Cross Domain Diffusion Model: A Generative AI Approach for Defect Pattern Segmentation","authors":"Yuanfu Yang;Min Sun","doi":"10.1109/TSM.2024.3472611","DOIUrl":"https://doi.org/10.1109/TSM.2024.3472611","url":null,"abstract":"In semiconductor manufacturing, defect detection is pivotal for enhancing productivity and yield. This paper introduces a novel weakly supervised method, the Implicit Cross Domain Diffusion Model (ICDDM), designed to tackle defect pattern segmentation challenges in the absence of detailed pixel-wise annotations. ICDDM employs a generative model to estimate the joint distribution of images depicting defect patterns and background circuits, formulating this estimation as a Markov Chain and optimizing it through denoising score matching. Building on this, we propose the Cross Domain Latent Diffusion Model (CDLDM), inspired by the Latent Diffusion Model, which simplifies the diffusion process into a lower-dimensional latent space to boost detection efficiency. Further enhancing our model, we introduce the Knowledge Distillation Cross Domain Diffusion Model (KDCDDM), which utilizes CDLDM as a teacher model and a Generative Adversarial Network (GAN) as a student model. This approach significantly accelerates the diffusion process by reducing the number of necessary denoising iterations while maintaining robust model performance. This suite of techniques offers a comprehensive solution for efficient and effective defect detection in semiconductor production environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"634-642"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Why Contour Averaging Works for SEM Metrology: Analysis and Validation","authors":"Jingxian Wei;Chenyu Xu;Sihai Zhang","doi":"10.1109/TSM.2024.3471635","DOIUrl":"https://doi.org/10.1109/TSM.2024.3471635","url":null,"abstract":"As the technology node in semiconductor manufacturing continuously shrinks, the etch-induced etch bias introduced during the etching process cannot be ignored and necessitates correction. The prevailing approach to addressing this issue is model-based etch bias correction. This method involves simulating the etching process by training an etch model that predicts the bias between the After Development Inspection (ADI) contour and the After Etch Inspection (AEI) contour. However, the reliability of the etch data for model training is compromised due to pattern shrinkage during Scanning Electron Microscope (SEM) imaging, which impairs the model’s prediction accuracy. To mitigate these issues, the contour averaging method is frequently employed, although it lacks thorough theoretical explanation and experimental verification. In this study, we validate the effectiveness of contour averaging theoretically and empirically. A relationship is derived between the prediction error of the etch model and the number of averaged contours, showing that contour averaging minimizes measurement errors of etch data. We also demonstrate the improved prediction accuracy of etch model using contour averaging, with both real and generated etch data.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"535-541"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Photoresist Spray Coating on Silicon Wafers With Acoustic Resonance Atomization","authors":"Jingjun Li;Xiukun Wang;Yadong Sun;Lei Zhang","doi":"10.1109/TSM.2024.3471738","DOIUrl":"https://doi.org/10.1109/TSM.2024.3471738","url":null,"abstract":"Aiming at the poor film evenness in conventional ultrasonic spraying coating methods, an acoustic resonance atomization (ARA) is proposed for spray coating on silicon wafers using an in-house experimental prototype. By modulating the acoustic pressure distribution in the optimized acoustic chamber, the ARA can achieve atomized photoresist droplets with \u0000<inline-formula> <tex-math>$sim 8.5~mu $ </tex-math></inline-formula>\u0000m in median diameter and concentrated droplet concentration. For mesoscale photoresist droplets, the uniform film of AZ P4620 photoresist is coated on silicon wafers by exploring and optimizing the substrate temperatures and spray velocity. The mechanism of uniform film formation by mesoscale photoresist droplets is explored. Smaller droplets can effectively fill the micro-gaps within the photoresist film layer, forming a dense and uniform film. The experimental results demonstrate that the employed coating process can obtain a controllable photoresist film thickness and evenness index of less than 5% with a high-quality film layer, which provides an alternative technological solution for the spray coating.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"576-582"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Density-Based Spatial Clustering of Applications With Noise (DBSCAN) for Probe Card Production for Advanced Quality Control of Wafer Probing Test","authors":"Chen-Fu Chien;Butsayarin Suwattananuruk","doi":"10.1109/TSM.2024.3468000","DOIUrl":"https://doi.org/10.1109/TSM.2024.3468000","url":null,"abstract":"Wafer probing test is crucial for selecting the known good dies via the probe card as the testing signal interface between the tester and the integrated circuits on the fabricated wafers. The consistency of probe cards is critical to ensure the integrity of the testing data. Motivated by realistic needs, this research aims to develop an effective approach for spatial clustering to select PCB materials while considering Time Domain Reflectometry (TDR) data. To estimate the validity, experiments are conducted with 20 datasets collected in real settings to compare the proposed DBSCAN with three spatial clustering models including Agglomerative Hierarchical Clustering (AHC), K-means, and Spectral Clustering. An empirical study is conducted in a lead semiconductor testing company in Taiwan for validation. The results have shown that the proposed approach can improve the impedance value of material selection by at least 15% for single-signal and 25% for differential signals, respectively. Thus, the proposed solution can effectively reduce intrinsic variance and enhance probing test integrity to reduce both the producer’s risk and the customer’s risk. Indeed, the developed solution is implemented to enhance virtual vertical integration for the semiconductor supply chain.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"567-575"},"PeriodicalIF":2.3,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sustainable Technologies for Responsible Products and a More Sustainable Future","authors":"S. Nicoleau;J.-L. Champseix;D. Tagarian;F. Boeuf;P. Quinio","doi":"10.1109/TSM.2024.3465603","DOIUrl":"https://doi.org/10.1109/TSM.2024.3465603","url":null,"abstract":"The impact of human activity on the environment is well documented. While citizens and responsible leaders aim at a more sustainable future, it is our duty as industrial companies to examine our products portfolio from its life cycle perspective. A promising approach is to use sustainable manufacturing technologies, that minimize negative environmental impact, while boosting the product benefits towards decarbonization objectives. This paper enriches our earlier description (Nicoleau et al., 2023) of STMicroelectronics approach in developing sustainable technologies. It starts by examining the global context while putting in perspective the definition of responsible products. Then we will go through the different phases of the product lifecycle by illustrating the involved processes during technology development and product manufacturing. And we will complete our Life Cycle Assessment methodology by illustrating the efforts in striving to reduce our ecological footprint towards our ambition of carbon neutrality by 2027.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"433-439"},"PeriodicalIF":2.3,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Overlay Measurement Algorithm for Moiré Targets Using Frequency Analysis","authors":"Hyunchul Lee;Hyunjin Chang;Hosung Woo;WonGu Lee","doi":"10.1109/TSM.2024.3431207","DOIUrl":"10.1109/TSM.2024.3431207","url":null,"abstract":"The miniaturization of semiconductor chips creates discrepancies between the designed node size and physical values. It has resulted in a tightened on-product overlay (OPO) budget and increased the demand for improved measurement noise reduction and accuracy in optical systems. A solution utilizing moiré targets can address such challenges by enabling the amplification of small misalignments that cannot be achieved with conventional overlay targets using an image-based overlay (IBO) estimator. However, moiré patterns formed within a layer introduce noise sources and problems owing to interference from the reflected light, adversely affecting the precision of overlay measurements and limiting the effective utilization of moiré patterns. We investigate the problems associated with moiré patterns in the IBO measurement method and propose a novel overlay measurement algorithm to mitigate the problems. The proposed algorithm increases the accuracy of the filtering method in the spatial frequency domain and improves the overlay precision by approximately 2% compared with conventional measurement algorithms. The proposed low-frequency selection algorithm and signal indexing algorithm effectively address the challenges posed by high-frequency problems and signal strength degradation in moiré patterns. The proposed practical solution achieves more accurate overlay measurements in semiconductor manufacturing, enabling better control and optimization of chip fabrication processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"489-498"},"PeriodicalIF":2.3,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance Evaluation of Supervised Learning Model Based on Functional Data Analysis and Summary Statistics","authors":"Yonghan Ju, Yung-Seop Lee","doi":"10.1109/tsm.2024.3452947","DOIUrl":"https://doi.org/10.1109/tsm.2024.3452947","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"58 1","pages":""},"PeriodicalIF":2.7,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine Learning-Based Universal Threshold Voltage Extraction of Transistors Using Convolutional Neural Networks","authors":"Hüsnü Murat Koçak;Jesse Davis;Michel Houssa;Ahmet Teoman Naskali;Jerome Mitard","doi":"10.1109/TSM.2024.3450286","DOIUrl":"10.1109/TSM.2024.3450286","url":null,"abstract":"The threshold voltage \u0000<inline-formula> <tex-math>$(V_{th})$ </tex-math></inline-formula>\u0000 enables us to measure the functionality of ultra-scaled field effect transistors (FETs) and plays a key role in the performance evaluation of devices. Although many \u0000<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>\u0000 extraction methods exist and are in use in the industry, selecting an optimized and universal method is still difficult. Additionally, these methods often rely on expert validation, which increases the time cost for researchers to optimize the extraction process. In this work, we propose a universal and autonomous machine learning model, specifically a convolutional neural network based \u0000<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>\u0000 extractor model. The novelty of this work lies in simultaneously processing gate, drain, source, and bulk currents combined with gate voltage to remove the dependency on setting boundaries for gate voltage. Additionally, the training dataset is composed of measurements coming from transistors of different technology nodes (Planar, MOSFET, FinFET, Gate-All-Around) to provide generalization. Our method produces significantly more accurate results than traditional ML algorithms by extracting \u0000<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>\u0000 in 3mV mean absolute error rate and is verified with different performance metrics.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"615-619"},"PeriodicalIF":2.3,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}