BDSD-Net: An Efficient and High-Precision Anomaly Detector for Real-Time Semiconductor Wafer Vision Inspection

Abstract

The advancement of integrated circuit fabrication processes has resulted in a concomitant increase in the complexity and frequency of surface defects on semiconductor wafers. This underscores the necessity for precise, real-time quality monitoring and control to enhance yield, cost-efficiency, and performance. Traditional automatic optical inspection (AOI) methods based on die-to-golden sample, die-to-die, or general deep learning-based semantic segmentation models often fail to meet these requirements due to insufficient detection accuracy, high false alarm rates, or inadequate throughput. To address these challenges, this paper proposes BDSD-Net, an efficient real-time detector that achieves state-of-the-art (SoTA) performance in wafer surface defect detection. Initially, a novel lightweight MVHNet backbone is developed, which seamlessly integrates the synergistic strengths of convolutional neural networks (CNNs) and Transformers within a ResNet-inspired architecture. Subsequently, an adaptive hybrid encoder is engineered to reduce the interference caused by intricate background patterns, thereby enhancing the accuracy of defect segmentation. This encoder includes an adaptive intra-scale feature interaction (ADFI) module that extracts more detailed high-level semantic information, and an adaptive multi-scale feature fusion (AMFF) module that effectively merges defect features across various scales. Moving away from high-complexity encoder structures, an efficient multi-scale residual fusion (EMRF) module is developed to narrow down the hypothesis space, thereby accelerating convergence. Finally, a knowledge distillation training strategy is also implemented to equip the lightweight model with the learning capabilities of more complex network models, thus enhancing its mean average precision (mAP) and frames per second (FPS) in inspection tasks. Extensive experimental results demonstrate the effectiveness of our method with data volume robustness, which achieves 88.2% and 88.9% mAP@0.5 on the semiconductor wafer and chip datasets. Moreover, compared to SoTA methods, our framework shows superior performance, achieving a compact model size of only 27 MB and a detection speed of 108.4 FPS. The demo code of this work is publicly available at https://github.com/Adiao2001/BDSD-Net/.