IEEE Transactions on Semiconductor Manufacturing最新文献_第3页

Reducing Datacenter Compute Carbon Footprint by Harnessing the Power of Specialization: Principles, Metrics, Challenges and Opportunities 利用专业化的力量减少数据中心计算的碳足迹：原则、指标、挑战和机遇

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-31 DOI: 10.1109/tsm.2024.3434331

Tamar Eilam, Pradip Bose, Luca P. Carloni, Asaf Cidon, Hubertus Franke, Martha A. Kim, Eun K. Lee, Mahmoud Naghshineh, Pritish Parida, Clifford S. Stein, Asser N. Tantawi

引用次数: 0

Wafer Dicing Vibration Investigation on Novel Wafer Mounting Techniques 新型晶片安装技术的晶片切割振动研究

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-29 DOI: 10.1109/tsm.2024.3435338

Mohd Syahrin Amri, Ghazali Omar, Mohd Syafiq Mispan, Fuaida Harun, MNB. Othman, N.A. Ngatiman, Masrullizam Mat Ibrahim

引用次数: 0

Comparison of Semiconductor Reverse Osmosis System Performance With Conventional and 3D Printed Feed Channels 使用传统和 3D 打印进料通道的半导体反渗透系统性能比较

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-26 DOI: 10.1109/tsm.2024.3430820

Christopher Kurth, Zhewei Zhang, Kevin Roderick, Jay Kendall Weingardt, Richard Lopez, Hwee Kiang, Peter Navaneethakrishnan, Deena Starkel

引用次数: 0

Plasma Etching Endpoint Detection in the Presence of Chamber Variations Through Nonlinear Manifold Learning and Density-Based Clustering 通过非线性积分学习和基于密度的聚类在腔室变化的情况下检测等离子刻蚀终点

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-26 DOI: 10.1109/tsm.2024.3434489

Chae Sun Kim, Hae Rang Roh, Yongseok Lee, Taekyoon Park, Chanmin Lee, Jong Min Lee

引用次数: 0

Boundless Engineering for Yield to Cope With the Complexity of High-Volume Manufacturing 无止境的产量工程，应对大批量生产的复杂性

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-15 DOI: 10.1109/tsm.2024.3428936

Giyoung Yang, Lay Hoon Loh, Emma Greer, Xiaodong Zhang, Shivendra Pandey, Saramma Varghese, Wee Hong Goh, Jianjun Cheng, Eric Hao Guan, Angelo Pinto

引用次数: 0

Quantitative Comparison of Simulation and Experiment Enabling a Lithography Digital Twin 实现光刻数字孪生的模拟与实验定量比较

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-12 DOI: 10.1109/tsm.2024.3427409

Yutong Xie, Benyamin Davaji, Ivan Chakarov, Sandy Wen, Michael Hargrove, David Fried, Peter C. Doerschuk, Amit Lal

引用次数: 0

A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111> 半导体单晶-硅生长的结构损失实时自动检测与停止规则

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-04 DOI: 10.1109/TSM.2024.3421926

Wheyming Tina Song;Yu-Fan Liao

{"title":"A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111>","authors":"Wheyming Tina Song;Yu-Fan Liao","doi":"10.1109/TSM.2024.3421926","DOIUrl":"10.1109/TSM.2024.3421926","url":null,"abstract":"The occurrence of the “structural-loss” defect during single-crystal silicon growth (SCSG) is a significant issue in semiconductor manufacturing. When structural-loss occurs, it signifies a deviation from the desired quality of single-crystal formation, leading to the need to halt the growth process. Currently, there is a lack of scholarly literature addressing the determination of an optimal stopping time to promptly halt the process upon the occurrence of the defect on-line. Our research makes a substantial contribution by addressing this gap in the SCSG process, specifically focusing on orientations <100> and <111>. The study utilizes advanced AI with YOLO-v7 and innovative approaches. These include precise annotation of crystal misorientation features through a comprehensive definition of structural-loss and novel labeling techniques, identification of optimal hyper-parameters through a robust design, and the implementation of effective stopping rule mechanisms. Significant progress has been achieved in decision-making through the implementation of the stoping time shift to terminate the SCSG process within an average of less than 3 minutes for <100> orientations (with a standard error of 0.3 minutes) and less than 5 minutes for <111> orientations (with a standard error of 0.5 minutes). The promising results indicate that the proposed approaches have the capability to substitute manual inspections, opening up possibilities for new perspectives in this particular field.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"304-315"},"PeriodicalIF":2.3,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141552962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN 基于多路径 DCNN 的混合缺陷模式晶片图识别与分类

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-26 DOI: 10.1109/TSM.2024.3418520

Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu

{"title":"Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN","authors":"Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu","doi":"10.1109/TSM.2024.3418520","DOIUrl":"10.1109/TSM.2024.3418520","url":null,"abstract":"The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"316-328"},"PeriodicalIF":2.3,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy 从 DSH 到扩展-DSH：基于解耦回归策略的芯片级化学机械平坦化 (CMP) 模型升级

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-25 DOI: 10.1109/TSM.2024.3418827

Qian Yue;Chen Lan

{"title":"DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy","authors":"Qian Yue;Chen Lan","doi":"10.1109/TSM.2024.3418827","DOIUrl":"10.1109/TSM.2024.3418827","url":null,"abstract":"Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"329-339"},"PeriodicalIF":2.3,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum 利用整个光学发射光谱对等离子体蚀刻过程中的关键尺寸进行虚拟测量

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-24 DOI: 10.1109/TSM.2024.3416844

Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic

{"title":"Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum","authors":"Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic","doi":"10.1109/TSM.2024.3416844","DOIUrl":"10.1109/TSM.2024.3416844","url":null,"abstract":"This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"363-372"},"PeriodicalIF":2.3,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0