IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2026.3716518","DOIUrl":"https://doi.org/10.1109/TSM.2026.3716518","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"C3-C3"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11644810","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Boundary-Aware Surrogate Model for Predicting Feature-Scale TiN Etching Profiles","authors":"Quanzhi Long;Fuqiang Zheng;Ting Yao;Xiaoming Shi;Xuqing Zhang;Dawei Gao","doi":"10.1109/TSM.2026.3695310","DOIUrl":"https://doi.org/10.1109/TSM.2026.3695310","url":null,"abstract":"In semiconductor manufacturing research, AI efforts mainly concentrate on virtual metrology and defect inspection, outputting scalars or labels rather than full cross-sectional morphology. Feature-scale plasma etch simulators remain the primary way to obtain the morphology by numerically evolving the etched front, but they require meticulous physical modeling and take tens of minutes per recipe. This cost and sensitivity make systematic process-window exploration and design–technology co-optimization (DTCO)-style iteration impractical. We propose a boundary-aware, time-conditioned surrogate model that maps six process parameters and absolute etch time to a 256×256 TiN cross-section. The model is a lightweight decoder trained with an edge-weighted composite loss and evaluated through a single unified boundary pipeline. We report recipe-level boundary-F1 and HD95 with right-continuous P90 tails, and treat pixel MSE/SSIM as secondary checks. On 80 TiN etch recipes (2.4 k frames) generated by Latin hypercube sampling, compared with a capacity-matched U-Net decoder, the surrogate model has reduced the mean HD95 value by about 10%, tightened the tail distribution (HD95 P90 from 1.047 px to 0.986 px), and lowered MSE by about 12%. Generating an entire about 30-frame trajectory for one recipe takes about 53 ms on a laptop-class GPU, which is about 3<inline-formula> <tex-math>$times 10{^{{4}}}$ </tex-math></inline-formula> times faster than a commercial topography solver that takes 28 min per recipe. These improvements can be attributed to absolute time conditioning, CoordConv-based spatial localization, and deep-supervised edge-weighted loss, offering the promise of near-interactive exploration of etching evolution hypotheses.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"540-548"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Edge Effect Compensation Algorithm for Eddy Current Endpoint Detection System in the CMP Process","authors":"Li Ting;Zhang Kang;Wu Jianwei;Tan Jiubin","doi":"10.1109/TSM.2026.3705753","DOIUrl":"https://doi.org/10.1109/TSM.2026.3705753","url":null,"abstract":"In the integrated circuit manufacturing process, the wafer profile control in the copper chemical mechanical planarization (Cu CMP) exhibits higher uncertainty compared to oxide chemical mechanical planarization, primarily due to the predominant influence of chemical reactions rather than mechanical friction. Real-time monitoring of copper film thickness using eddy current technology is an effective method for ensuring the accuracy of polishing pressure feedback adjustment system in CMP process. However, the edge effect causes attenuation of the eddy-current signal, distorting the measurement of wafer edge thickness and increasing the risk of residual defects in Cu CMP. The objective of this study is to investigate the mechanism of eddy current edge effect through numerical simulation and online experiments, and propose an optimization methodology applicable in IC manufacturing. The key factors that were evaluated include the coil and ferrite structure, excitation frequency of the eddy current sensor, position of wafer radius, thickness of copper film, and kinematic relationship between sensor and wafer. A compensation coefficient matrix is proposed to optimize measurement distortion caused by the edge effects. The feasibility and accuracy of this method have been verified in the practical application of the Cu CMP process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"549-554"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Attention-Based Deep Learning for Multi-Target Prediction of Process Time and Tool Availability in Large-Scale Semiconductor Fabs","authors":"T. E. Korabi;G. Goossen;A. Kaushik;J. van Heugten;A. Raghuvanshi;J. Bédorf;S. Chakravorty;D. Pabst;S. Ramakrishnan;J. DeLong;T. Hewlett;A. Ang;A. Wong;K. Soh;S. Velasquez;H. Mogra","doi":"10.1109/TSM.2026.3706122","DOIUrl":"https://doi.org/10.1109/TSM.2026.3706122","url":null,"abstract":"Precise prediction of processing time (PT) and machine availability is critical for optimizing fabrication throughput. This paper presents a generalized, attention-based deep neural network designed to capture non-linear tool dynamics and high-dimensional categorical dependencies. Unlike rigid statistical baselines, our framework adapts to multiple prediction targets, including equipment-level process completion and granular chamber-level availability. Deployed in multiple GlobalFoundries semiconductor fabrication plants, the model demonstrates a 50% to 80% reduction in mean absolute error (MAE) compared to historical averages. Production results confirm a 2% to 3% increase in moves per productive hour and a 3% to 7% sustained increase in chamber utilization across a majority of the tools that we tested with. These results validate the strength of machine learning methods in enabling advanced parallel loading and just-in-time dispatching strategies.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"395-401"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"D2Seg: Dual-Image Differential Interleaved Semantic Segmentation Network for Accurate Semiconductor Wafer Surface Defect Detection","authors":"Zhaolei Diao;Shuang Mei;Jiangtao Cheng;Yuzhang He;Guojun Wen","doi":"10.1109/TSM.2026.3689722","DOIUrl":"https://doi.org/10.1109/TSM.2026.3689722","url":null,"abstract":"Optical inspection of surface defects on patterned wafers plays a crucial role in yield management and control within advanced semiconductor manufacturing. Although several vision-based approaches have been proposed for this challenging task, they often struggle with fine edge segmentation, sensitivity to noise, and limited generalization to unseen defect types. To address these issues, we propose a novel dual-image-based segmentation network, termed D2Seg, for high-precision wafer surface defect inspection. The framework operates in two stages. First, a Backbone Reinforcement (BR) strategy is introduced to enhance the encoder’s robustness under low-contrast conditions, thereby improving the extraction of high-quality features. Second, a Siamese encoder-decoder architecture is designed to learn discriminative representations by comparing paired images, thereby enabling accurate defect-boundary segmentation and improved generalization. Specifically, we propose a Neighbor Feature Aggregation (NFA) module to achieve efficient and robust cross-scale and cross-location correlation modeling, along with high-level feature enhancement. Additionally, a set of Difference Information Extraction (DIE) modules is integrated to capture defect-related features at multiple scales, encouraging the network to suppress non-defect invariants while highlighting defect regions. Furthermore, a Scale Self-Attention Refinement (SAR) module is designed to augment the perception of defect areas, thereby refining the detection of subtle edges. Experimental results on two wafer-defect datasets collected from real production lines demonstrate that D2Seg outperforms the compared methods, achieving mIoU values of 94.12% and 87.97% and mPA values of 95.83% and 91.29%, respectively. These results demonstrate the robustness and effectiveness of the proposed method for detecting surface defects on patterned wafers, particularly in identifying small defects and producing precise edge segmentation.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"453-463"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shape-Based Mask Process Correction Method With Staged Pattern Fragmentation and Dose Adjustment for Curvilinear Masks","authors":"Chun-Hung Liu;Yu-Lin Chung;Sheng-Kai Wong;Yu-Tang Sun;Ze-An Ding","doi":"10.1109/TSM.2026.3704375","DOIUrl":"https://doi.org/10.1109/TSM.2026.3704375","url":null,"abstract":"Conventional shape-based curvilinear mask process correction (CL-MPC) methods designed for suppressing proximity effects commonly adopt distance-based fragmentation (DBF) and curvature-based fragmentation (CBF). While DBF ensures high correction accuracy, it incurs substantial computational cost. In contrast, CBF improves efficiency but compromises geometric detail and correction accuracy. To address the limitations of these methods while preserving their strengths, this study presents a shape-based CL-MPC method that combines two-stage edge fragmentation and dose-adjustment strategies. The fragmentation process employs different fixed distances in two stages to generate uniform target-point distributions at varying densities, enhancing both correction efficiency and accuracy; coarse fragmentation is applied in the first stage and finer fragmentation is applied in the second stage. The dose-adjustment strategy utilizes both the target point density and local pattern density to enhance correction convergence, edge energy slope, and resistance to process variation. By integrating multi-stage fragmentation with dose adjustment, the proposed method reduces the computational cost of DBF and addresses the accuracy limitations of CBF, thereby considerably improving pattern fidelity, computational efficiency, and anti-process variation ability in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"487-497"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Virtual Metrology via Intervention-Anchored Hidden-State Decomposition for Post-Maintenance Recovery and Recipe Migration","authors":"Chin-Yi Lin;Tzu-Liang Tseng;Tsung-Han Tsai","doi":"10.1109/TSM.2026.3713125","DOIUrl":"https://doi.org/10.1109/TSM.2026.3713125","url":null,"abstract":"Virtual metrology (VM) is widely used to infer wafer quality from equipment and process data, but its industrial value often deteriorates after preventive maintenance, chamber cleaning, recipe migration, or tool transfer because predictor-centric models indicate degraded accuracy without revealing which hidden process factor has changed. This paper proposes intervention-anchored hidden-state virtual metrology (I2S-VM), which uses naturally logged fab events as weak supervision to decompose latent dynamics into tool-state, recipe-state, and wafer-level components for joint metrology prediction and actionable state attribution. The framework combines sequential encoding of fault detection and classification (FDC) traces, intervention-aligned transition learning, cross-tool state-swap consistency under matched recipe context, and self-supervised multivariate time-series learning under sparse metrology. A population-level structural analysis suggests that, under selective interventions and sufficiently rich matched pairs, the learned decomposition is recoverable up to block-wise invertible transformations. Experiments on a confidential industrial epitaxial growth dataset from a German semiconductor manufacturer, containing 24,960 wafers, 4,320 labeled wafers, four tools, and eight chambers, show that I2S-VM achieves 1.24ÅMAE and 1.69ÅRMSE in the seen-tool/seen-recipe setting and consistently outperforms strong baselines in post-maintenance recovery, low-shot recipe adaptation, and zero-shot cross-tool transfer. These results indicate that intervention-anchored hidden-state learning can make VM not only more accurate but also more actionable for maintenance recovery, recipe qualification, and sister-tool deployment.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"572-589"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inter-Layer Edge Placement Error Measurement via Backscattered Electron Imaging for Process Window Improvement","authors":"Pei Liu;Yuyang Bian;Yu Zhang;Biqiu Liu;Ying Dong;Ming Tian;Chiunghan Yeh;Baojun Zhao;Mingzhi Chen;Chih Cheng Chang;Jian Cao;Peiyu Chen;Tsung Yen Pan;Wenchen Guo;Jiajie Yu;Qingqing Sun;David Wei Zhang;Lin Chen","doi":"10.1109/TSM.2026.3704464","DOIUrl":"https://doi.org/10.1109/TSM.2026.3704464","url":null,"abstract":"The metric of edge placement error (EPE) has been widely used to evaluate pattern placement deviations, and EPE-based analysis has been extensively applied to improve patterning control and enhance the process window in semiconductor manufacturing. However, the implementation of EPE analysis as a standard methodology in real production remains unclear. Most studies focus on characterizing the discrepancy between the actual edge placement of a pattern and its designed location. However, significant challenges remain in statistically processing these data to evaluate the process window. In our study, the method of inter-layer EPE analysis is demonstrated under the backscattered electron (BSE) imaging. A scanning electron microscope (SEM) equipped with a high-efficiency BSE detector and a secondary electron (SE) detector is used during contact tungsten chemical-mechanical planarization (CMP) to examine the features of the contact and gate. The edge distance (ED) is extracted from the SEM images, enabling the evaluation of the primary contributors to process window improvement by measuring the edge-to-edge distance between the gate and contact. A comprehensive methodology has been developed based on this approach.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"498-502"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148694821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Two-Level Pareto-Based Hierarchical Reinforcement Learning for Dynamic Multi-Objective Scheduling in Semiconductor Fabs","authors":"Chin-Yi Lin;Tzu-Liang Tseng;Tsung-Han Tsai","doi":"10.1109/TSM.2026.3704324","DOIUrl":"https://doi.org/10.1109/TSM.2026.3704324","url":null,"abstract":"This paper addresses the critical challenges of dynamic, multi-objective scheduling in semiconductor wafer manufacturing, where decision makers must balance conflicting goals such as throughput, yield, cycle time, and energy efficiency amid frequent disruptions and large-scale complexity. We propose a novel Pareto-based Hierarchical Multi-Objective Reinforcement Learning (PH-MORL) framework, which integrates the exploration of Pareto-optimal trade-offs with a hierarchical decision structure. The high-level agent adaptively determines global objective pReferences by referencing a continuously maintained Pareto archive, capturing a diverse set of non-dominated solutions. These preferences are then broadcast to low-level agents that learn fine-grained scheduling actions for individual workstations. Through this dual-layer synergy, PH-MORL overcomes the limitations of fixed-weight multi-objective methods and single-layer learning architectures, enabling real-time reconfiguration of scheduling strategies in response to machine failures, urgent orders, or yield fluctuations. The proposed framework not only discovers a broad spectrum of feasible performance compromises but also dynamically coordinates local and global decision making. Our formal analysis establishes tracking and stability properties under standard finite-state stochastic-approximation and contraction assumptions, while extensive discrete-event simulation experiments in realistic wafer-fab settings demonstrate improved dynamic scheduling trade-offs, real-time inference feasibility, and competitive performance against rolling-horizon NSGA-II/III baselines. We further provide CPU-only end-to-end inference measurements that include state-feature assembly, feasible-action enumeration and masking, neural-network inference, rule-based safety filtering, and dispatch commitment. Across 30 independent 240-hour replications, PH-MORL achieves 15.7 ms mean latency, 31.5 ms p95 latency, 50.3 ms p99 latency, and 182.0 ms maximum latency, remaining well below the 1 s dispatching budget required for real-time dispatching in modern 300 mm fabs. These results highlight PH-MORL’s potential for scalable and flexible optimization in modern semiconductor manufacturing, and its generalizable structure paves the way for broader adoption in other complex, multi-objective industrial environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"590-613"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Run-to-Run Control of Chemical Mechanical Polishing Head With Adjustable Partition Pressure Based on Deep Reinforcement Learning","authors":"Yuxiang Li;Wentao Liu;Guoshan Zhang","doi":"10.1109/TSM.2026.3686202","DOIUrl":"https://doi.org/10.1109/TSM.2026.3686202","url":null,"abstract":"The polishing head is one of the most important components in the chemical mechanical polishing (CMP) process, used to achieve an ultra-smooth surface on the wafer. Due to the effect of the retaining ring and the replacement of the polishing pad, the polishing process is subjected to drift and shift interference. The CMP head with partition pressure is designed to exert pressure separately according to the situation of the wafer edge being affected, and compensate for the disturbance caused by slight changes in different areas inside the wafer. A run-to-run (R2R) control method based on deep reinforcement learning (DRL) is proposed to adjust the process parameters between runs. A dual experience replay mechanism is adopted to effectively utilize the interactive information between the agent and the CMP environment designed. Simulation experiments are conducted under the conditions of pad drift and pad replacement. Results demonstrate that the proposed method achieves superior performance in MRR optimization. The WIWNU is optimized to a minimum of 0.3%, and the maximum difference of the polished wafer thickness under the two experimental conditions is below 25 nm. Thus, the proposed method can effectively compensate for the drift caused by equipment aging, and can sense environmental changes and adjust process parameters.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 3","pages":"555-564"},"PeriodicalIF":2.5,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148695061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}