IEEE Transactions on Semiconductor Manufacturing最新文献_第3页

Unsupervised Representation Learning and Explainable Clustering for Wafer Map Pattern Analysis 用于晶圆图模式分析的无监督表示学习和可解释聚类

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-12 DOI: 10.1109/TSM.2025.3579031

Itilekha Podder;Marco Miller;Tamas Fischl;Udo Bub

{"title":"Unsupervised Representation Learning and Explainable Clustering for Wafer Map Pattern Analysis","authors":"Itilekha Podder;Marco Miller;Tamas Fischl;Udo Bub","doi":"10.1109/TSM.2025.3579031","DOIUrl":"https://doi.org/10.1109/TSM.2025.3579031","url":null,"abstract":"As wafer maps become increasingly complex and high-dimensional, conventional clustering methods often fail to uncover subtle but meaningful defect patterns critical for yield enhancement and fault diagnosis in semiconductor manufacturing. We present an unsupervised clustering framework tailored to wafer map analysis, combining a convolutional autoencoder for automated feature extraction with principal component analysis for dimensionality refinement. Additionally, we incorporate improved deep embedded clustering, which augments the autoencoder with a clustering-oriented Kullback-Leibler divergence loss to learn compact and confident latent representations. Using standard clustering metrics and extensive visualization, our method is evaluated on two private industrial micro-electromechanical systems datasets and the public MIR-WM811K dataset. Unlike prior approaches, we introduce a comprehensive evaluation strategy that includes (i) cluster confidence and entropy distributions to assess prediction determinism, (ii) semi-supervised scoring for structure-aware validation, and (iii) interpretable visual tools, such as SHapley Additive exPlanations maps, gradient-weighted class activation mapping overlays, and average cluster profiles to support human-in-the-loop decision-making. Results show that our framework consistently outperforms baseline methods, including pretrained visual models like DINOv2 and TIMM-ResNet, in both clustering quality and interpretability. By aligning unsupervised representations with domain-specific failure semantics, the proposed pipeline enables more transparent and actionable analysis of wafer maps. Integrating automated feature learning, probabilistic confidence modelling, and visual attribution offers a robust path toward root-cause identification and process optimization in modern semiconductor fabrication.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"693-708"},"PeriodicalIF":2.3,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Process Sensitivity of 355 nm-Laser-Induced High-Concentration Aluminum Doping for P-Type Layer in Semi-Insulating 4H-SiC 355 nm激光诱导高浓度铝掺杂半绝缘4H-SiC p型层的工艺灵敏度

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-09 DOI: 10.1109/TSM.2025.3577624

Chang-Shan Shen;Wei-Chi Aeneas Hsu;Ming-Chun Hsu;Hong-Yi Guo;Yu-Xian Liu;Hua-Yan Chen;Guan-Jie Liu;Duong Minh Hoang;Tsun-Hsu Chang

{"title":"Process Sensitivity of 355 nm-Laser-Induced High-Concentration Aluminum Doping for P-Type Layer in Semi-Insulating 4H-SiC","authors":"Chang-Shan Shen;Wei-Chi Aeneas Hsu;Ming-Chun Hsu;Hong-Yi Guo;Yu-Xian Liu;Hua-Yan Chen;Guan-Jie Liu;Duong Minh Hoang;Tsun-Hsu Chang","doi":"10.1109/TSM.2025.3577624","DOIUrl":"https://doi.org/10.1109/TSM.2025.3577624","url":null,"abstract":"The advancement of high-power 4H-SiC devices demands innovative solutions to address doping challenges. This study introduces a 355 nm DPSS Nd:YAG laser scanning doping as a method for aluminum doping and surface modification in semi-insulating 4H-SiC, addressing the limitations of conventional ion-implantation techniques. Through a systematic investigation of laser fluence, we identify process windows that balance carrier activation and material properties. At a fluence threshold of 2.588 J/cm2, effective Al activation was achieved, while higher fluences induce polysilicon formation, as verified by Raman, GIXRD, SIMS, and Hall measurements. Remarkably, laser processing generates a multilayer surface structure—graphite, polysilicon, poly-SiC, and 4H-SiC—potentially reducing the barrier height. This method demonstrates significant potential for fabricating high-performance p-type contacts on 4H-SiC. These findings highlight the sensitivity and versatility of laser doping, offering critical insights into next-generation SiC fabrication strategies.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"728-733"},"PeriodicalIF":2.3,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast and High-Precision Temperature Control in Semiconductor Vertical Furnace via Iterative Experiments 基于迭代实验的半导体垂直炉快速高精度温度控制

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-04 DOI: 10.1109/TSM.2025.3576496

Christian Milleneuve Budiono;Akira Hirata;Tatsuya Yamaguchi;Takafumi Koseki;Wataru Ohnishi

{"title":"Fast and High-Precision Temperature Control in Semiconductor Vertical Furnace via Iterative Experiments","authors":"Christian Milleneuve Budiono;Akira Hirata;Tatsuya Yamaguchi;Takafumi Koseki;Wataru Ohnishi","doi":"10.1109/TSM.2025.3576496","DOIUrl":"https://doi.org/10.1109/TSM.2025.3576496","url":null,"abstract":"The semiconductor vertical furnace is a key component in semiconductor manufacturing, used for heat treatment processes such as oxidation, layer deposition, and annealing. Improving the speed of temperature control in this equipment is critical for increasing productivity, particularly by shortening the time required for large temperature changes, known as thermal ramps. Although modeling a linear time-invariant (LTI) system is effective around a fixed operating temperature, it becomes inaccurate during rapid heating and cooling processes that involve large temperature changes, especially when faster control performance is required. As a result, conventional model-based control methods often fail to deliver both fast and accurate temperature regulation in practical scenarios. The aim of this paper is to develop a data-driven approach that enables high-speed, high-precision temperature control in a semiconductor vertical furnace. The proposed method is based on an iterative experimental procedure that refines the control model using actual measurement data. Experimental results show that the approach achieves the target temperature accurately within just four iterations. Compared to the conventional Linear-Quadratic-Gaussian (LQG) control method, it reduces the settling time to within ±1°C of the setpoint by 18% and lowers energy consumption by 20%. These findings demonstrate that the proposed data-driven method enables faster, more accurate, and more energy-efficient temperature control in semiconductor vertical furnaces.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"478-486"},"PeriodicalIF":2.3,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11023613","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Physics-Informed Machine Learning-Based Edge Detection for SEM Images 基于物理的机器学习的扫描电镜图像边缘检测

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-03 DOI: 10.1109/TSM.2025.3576269

Yi Fang;Chun Wang;Sihai Zhang

{"title":"Physics-Informed Machine Learning-Based Edge Detection for SEM Images","authors":"Yi Fang;Chun Wang;Sihai Zhang","doi":"10.1109/TSM.2025.3576269","DOIUrl":"https://doi.org/10.1109/TSM.2025.3576269","url":null,"abstract":"The Scanning Electron Microscope (SEM) images of Random Access Memory (RAM) chips contain valuable process-related information, particularly at the edges, which can provide critical insights for hotspot detection and Line Edge Roughness (LER) measurement. However, significant noise and low grayscale variation in SEM images often lead to edge omissions and misdetections. In this paper, we introduce the concept of the SEM Interlayer Effect (SIE), based on empirical observations and theoretical analysis, to address these challenges. Leveraging insights from SIE, we propose a novel Physics-Informed Edge Detection (PIED) method, which enhances the underlying neural network architecture and incorporates a hierarchical weighted loss function. Based on the real-world SEM image dataset from RAM production, PIED achieves a superior Optimal Dataset Scale (ODS) F-measure compared to the Canny edge detector, improving from 0.9001 to 0.9701—a 7.8% increase. This demonstrates that even in the absence of ground truth, PIED significantly enhances edge detection performance, which is crucial for improving process control in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"579-587"},"PeriodicalIF":2.3,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ar/N₂ Gas Flow Rate Dependence on the Ferroelectric HfNₓ Thin Film Formation by ECR-Plasma Sputtering Ar/ n2气体流速对铁电HfNₓecr -等离子溅射薄膜形成的影响

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-02 DOI: 10.1109/TSM.2025.3575588

Kangbai Li;Shun-Ichiro Ohmi

{"title":"Ar/N₂ Gas Flow Rate Dependence on the Ferroelectric HfNₓ Thin Film Formation by ECR-Plasma Sputtering","authors":"Kangbai Li;Shun-Ichiro Ohmi","doi":"10.1109/TSM.2025.3575588","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575588","url":null,"abstract":"In this paper, the Ar/N2 gas flow rate dependence on the ferroelectric HfNx (x>1) formed by electron cyclotron resonance (ECR)-plasma sputtering was investigated. The equivalent oxide thickness (EOT) of 2.7 nm was obtained with Ar/N2 gas flow rate of 8/7 sccm followed by the 400°C/5 min post metallization annealing (PMA) in N2. The EOT was increased to 4.2 nm with the deposition of the Ar/N2 gas flow rate of 14/16 sccm. The density of interface states (Dit) was found to be as low as <inline-formula> <tex-math>$2.0times 10{^{{11}}}$ </tex-math></inline-formula> <inline-formula> <tex-math>${mathrm {cm}}^{-2}$ </tex-math></inline-formula><inline-formula> <tex-math>${mathrm {eV}}^{-1}$ </tex-math></inline-formula>. The P-V results demonstrate that a remanent polarization (2Pr) of <inline-formula> <tex-math>$6.6~mu $ </tex-math></inline-formula>C/cm2, and positive-up negative-down measurement showed the switching polarization of <inline-formula> <tex-math>$4.7~mu $ </tex-math></inline-formula>C/cm2 at an Ar/N2 flow rate of 8/7 sccm, which is high enough for metal-ferroelectric-Si field-effect transistor (MFSFET) application.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"459-462"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MXenes as a Tool to Control p-Type Conductivity in ZnO Thin Film MXenes作为控制ZnO薄膜p型电导率的工具

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-02 DOI: 10.1109/TSM.2025.3575857

Lucky Agarwal;Ajay Kumar Dwivedi;Tulika Bajpai;Uvanesh Kasiviswanathan;Shweta Tripathi

引用次数: 0

Metal Contamination Behavior on Silicon Dioxide Surface Rinsed With Deionized Water Containing Ultra-Trace Metal During Single-Wafer Cleaning 单晶圆清洗过程中含超微量金属的去离子水冲洗二氧化硅表面的金属污染行为

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-06-02 DOI: 10.1109/TSM.2025.3575743

K. Tsutano;T. Mawaki;Y. Shirai;R. Kuroda

{"title":"Metal Contamination Behavior on Silicon Dioxide Surface Rinsed With Deionized Water Containing Ultra-Trace Metal During Single-Wafer Cleaning","authors":"K. Tsutano;T. Mawaki;Y. Shirai;R. Kuroda","doi":"10.1109/TSM.2025.3575743","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575743","url":null,"abstract":"Metal contamination control in semiconductor manufacturing processes is important because it affects device reliability and yield. The metal contamination control value in deionized water (DIW) is required at the pg/L level for advanced device manufacturing. However, previous studies on metallic contamination proved insufficient owing to their utilization of highly concentrated solutions at a <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>g/L level with batch rinsing processes. In this study, we investigated the contamination behavior of metal impurities at the pg/L level in DIW on the silicon dioxide (SiO2) surface during a single-wafer cleaning process. We found that Al, Ti, Fe, Zn, and Ga were highly adsorbed for the <inline-formula> <tex-math>$SiO_{2}$ </tex-math></inline-formula> surface, and these surface concentrations were positively correlated with the concentration in DIW and the rinse time. Whereas the adsorption behavior of these metals affected by rinse fluid parameters such as the rotation speed and the flow rate. The adsorption probability increased owing to thinning of the liquid-firm thickness and increasing radial velocity. Furthermore, the metal adsorption ratio was decreased with thinning boundary-layer thickness. Herein, we provide new insights into the pertinence of reducing metal concentrations in DIW and optimizing fluid parameters during a single-wafer cleaning to prevent metal contamination for advanced the semiconductor manufacturing process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"492-498"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DPFEE-Net: Enhancing Wafer Defect Classification Through Dual-Path Neural Architecture DPFEE-Net：通过双路神经网络架构增强晶圆缺陷分类

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-04-24 DOI: 10.1109/TSM.2025.3564051

Hongxu Li;Jie Ren;Teng Wu;Yonghong Zhang;Jianhua Chang;Hongen Yang;Ronghua Chi

{"title":"DPFEE-Net: Enhancing Wafer Defect Classification Through Dual-Path Neural Architecture","authors":"Hongxu Li;Jie Ren;Teng Wu;Yonghong Zhang;Jianhua Chang;Hongen Yang;Ronghua Chi","doi":"10.1109/TSM.2025.3564051","DOIUrl":"https://doi.org/10.1109/TSM.2025.3564051","url":null,"abstract":"Wafer defect detection and classification are essential for ensuring the quality of semiconductor wafers, optimizing production efficiency. However, existing methods often fail to process shallow and deep feature information concurrently, restricting their capacity to utilize multi-level features for accurate classification. To overcome this limitation, this paper introduces a novel dual-path architecture, DPFEE-Net, which integrates PeleeNet’s dense connection structure and multi-channel feature fusion techniques with the deep feature extraction capabilities of Convolutional Neural Networks (CNNs). By combining these two approaches, DPFEE-Net effectively captures both shallow and deep features, enhancing the detection of critical wafer surface defect patterns. Additionally, squeeze-and-excitation (SE) attention mechanism is incorporated, enabling the model to prioritize defect-prone areas in images, further improving classification accuracy. Experimental results demonstrate that DPFEE-Net achieves a remarkable average accuracy of 96.8% on the WM-811K dataset, surpassing existing methods such as WM-PeleeNet, WDD-SCA and MobileNetV2. Moreover, the model delivers superior detection performance with reduced computational complexity and parameter requirements, making it highly suitable for practical deployment in production environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"605-611"},"PeriodicalIF":2.3,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unsupervised Image Demoiréing With Self-Consistent GAN for TFT-LCD Defect Recognition 基于自一致GAN的TFT-LCD缺陷识别的无监督图像分解

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-04-17 DOI: 10.1109/TSM.2025.3561919

Tsung-Ta Hsieh;Jui-Hsin Hsiao;Chia-Yen Lee;Hung-Kai Wang

引用次数: 0

An Alternative PECVD Chamber Cleaning Gas of COF2 for Low-GWP Consideration 考虑低gwp的COF2替代PECVD室清洁气体

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-04-10 DOI: 10.1109/TSM.2025.3559471

Ah Hyun Park;Yeonjin Lee;Seyun Jo;Sang Jeen Hong

{"title":"An Alternative PECVD Chamber Cleaning Gas of COF2 for Low-GWP Consideration","authors":"Ah Hyun Park;Yeonjin Lee;Seyun Jo;Sang Jeen Hong","doi":"10.1109/TSM.2025.3559471","DOIUrl":"https://doi.org/10.1109/TSM.2025.3559471","url":null,"abstract":"Continuous deposition processes in PECVD environments are critical for ensuring the uniformity and reproducibility of thin films across various applications. Silicon dioxide (SiO2), widely used in these processes for its excellent properties, can leave residual materials in PECVD chambers, leading to material buildup that compromises process consistency and reproducibility. A representative example of compromised process consistency and reproducibility is found in the manufacturing of 3D-NAND flash memory, which involves oxide-nitride (ON) stacking processes. Effective chamber cleaning is essential to ensure consistent and reproducible performance in continuous deposition processes. Nitrogen trifluoride (NF3), a commonly used as chamber cleaning gas, is expected to be newly belong to the greenhouse gas regulations due to its high global warming potential (GWP), which may pose both environmental and industrial risks. In this study, we explored the potential of carbonyl fluoride (COF2) as an alternative chamber cleaning gas with low GWP, albeit with an inferior cleaning rate compared to NF3. This study investigates gas dissociation in the plasma environment and analyzes plasma species and changes in the deposited film surface affecting the cleaning rate. Based on the results, proposed improvements are made to the cleaning process design for COF2, considering factors influencing plasma enhanced chemical vapor deposition (PECVD) chamber cleaning efficiency.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"596-604"},"PeriodicalIF":2.3,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0