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IEEE Transactions on Semiconductor Manufacturing最新文献

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Guest Editorial Special Section on the 2025 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH) 2025年化合物半导体制造技术国际会议（CS-MANTECH）特邀编辑专区
IF 2.5 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-10-31 DOI: 10.1109/TSM.2025.3620505
Patrick Fay
{"title":"Guest Editorial Special Section on the 2025 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH)","authors":"Patrick Fay","doi":"10.1109/TSM.2025.3620505","DOIUrl":"https://doi.org/10.1109/TSM.2025.3620505","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"743-743"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223046","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Laser Direct Writing Lithography-Enabled Fan-Out Packaging Method for Self-Adapting LED Position Deviations 自适应LED位置偏差的激光直写光刻扇出封装方法
IF 2.5 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-10-07 DOI: 10.1109/TSM.2025.3618470
Zongtao Li;Zhouan Wang;Jianheng Guo;Hesheng Liu;Jiasheng Li
{"title":"Laser Direct Writing Lithography-Enabled Fan-Out Packaging Method for Self-Adapting LED Position Deviations","authors":"Zongtao Li;Zhouan Wang;Jianheng Guo;Hesheng Liu;Jiasheng Li","doi":"10.1109/TSM.2025.3618470","DOIUrl":"https://doi.org/10.1109/TSM.2025.3618470","url":null,"abstract":"Fan-out packaging (FOP) is promising for Mini/Micro-LED manufacturing, while chip misalignment occurs during the transferring process owing to the insufficient placement accuracy and the mismatched thermal expansion of packaging materials. This position deviation leads to interconnect misalignment between the redistribution layer (RDL) and chip electrodes, ultimately reducing packaging yield. This paper proposes a laser direct writing lithography (LDWL)-enabled FOP method to self-adapt the LED chip position deviation. The LDWL pattern is generated by machine vision according to the actual chip positions, ensuring precise interconnection between the RDL and chip electrodes. The proposed method has been successfully used to manufacture FOP LED devices, preserving excellent optoelectronic and mechanical performances, with the chip deflection tolerance of ±10° and the line width of approximately <inline-formula> <tex-math>$25~mu $ </tex-math></inline-formula> m. Our LDWL-FOP method can effectively compensate for the chip misalignment during the packaging process, showing great potential for the high-yield manufacturing of Mini/Micro-LED chips.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"812-817"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation and Modeling of Low Value Comb Resistors 低值梳状电阻器的评估与建模
IF 2.5 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-08-21 DOI: 10.1109/TSM.2025.3601537
Peter J. Zampardi;Quinn Davenport;Leonard Hayden
{"title":"Evaluation and Modeling of Low Value Comb Resistors","authors":"Peter J. Zampardi;Quinn Davenport;Leonard Hayden","doi":"10.1109/TSM.2025.3601537","DOIUrl":"https://doi.org/10.1109/TSM.2025.3601537","url":null,"abstract":"In power amplifier design, designers often use low value resistors where there are one or more ballast transistors per PA cell. Constant pressure to reduce die size means we would like the most compact solution as possible. In this work, we demonstrate low value “comb” or “interdigitated” resistors and present a simple model for them. A key feature of the model was finding the resistive contribution of the chamfered corners. These resistors also show significant improvement in variation compared to semiconductor resistors normally used in design.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"790-795"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel Batch Scheduling With Incompatible Job Families via Constraint Programming 基于约束规划的不兼容作业族并行批调度
IF 2.5 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-08-25 DOI: 10.1109/TSM.2025.3601510
Jorge A. Huertas;Pascal Van Hentenryck
{"title":"Parallel Batch Scheduling With Incompatible Job Families via Constraint Programming","authors":"Jorge A. Huertas;Pascal Van Hentenryck","doi":"10.1109/TSM.2025.3601510","DOIUrl":"https://doi.org/10.1109/TSM.2025.3601510","url":null,"abstract":"This paper addresses the incompatible case of parallel batch scheduling, where compatible jobs belong to the same family, and jobs from different families cannot be processed together in the same batch. The state-of-the-art constraint programming (CP) model for this problem relies on specific functions and global constraints only available in a well established commercial CP solver. This paper expands the literature around this problem by proposing four new CP models that can be implemented in commercial and open-source solvers: a new model that relies on automaton constraints, and three alternative models that integrate assignment and scheduling decisions with different strategies and global constraints. Extensive computational experiments on standard test cases under multiple objectives and multiple solvers demonstrate the implementation flexibility and competitive performance of the proposed models.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"901-916"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications 《IEEE电子器件学报：用于射频、功率和光电子应用的超宽带隙半导体器件》特刊征文
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-10-31 DOI: 10.1109/TSM.2025.3622883
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications","authors":"","doi":"10.1109/TSM.2025.3622883","DOIUrl":"https://doi.org/10.1109/TSM.2025.3622883","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"935-936"},"PeriodicalIF":2.3,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223045","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes 《IEEE电子设备学报：高级节点的可靠性》特刊征文
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-10-31 DOI: 10.1109/TSM.2025.3622881
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TSM.2025.3622881","DOIUrl":"https://doi.org/10.1109/TSM.2025.3622881","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"933-934"},"PeriodicalIF":2.3,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223071","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Semiconductor Manufacturing Information for Authors IEEE半导体制造信息汇刊
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-10-31 DOI: 10.1109/TSM.2025.3622905
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2025.3622905","DOIUrl":"https://doi.org/10.1109/TSM.2025.3622905","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11223047","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving RF Magnetron Sputter Parameters for a Piezoelectric AlN Thin Film Deposition 改进压电AlN薄膜沉积的射频磁控溅射参数
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-10-20 DOI: 10.1109/TSM.2025.3623907
S. Atheeth;H. B. Chandan;N. Trishul;Manish Arora
{"title":"Improving RF Magnetron Sputter Parameters for a Piezoelectric AlN Thin Film Deposition","authors":"S. Atheeth;H. B. Chandan;N. Trishul;Manish Arora","doi":"10.1109/TSM.2025.3623907","DOIUrl":"https://doi.org/10.1109/TSM.2025.3623907","url":null,"abstract":"This paper reports on the parameters that affect the crystalline quality of Aluminium Nitride (AlN) thin film grown using the RF magnetron sputtering process. AlN film of 1-micron thickness is the piezoelectric material of choice in the fabrication of a high-frequency resonating structure. Substrate temperature, RF power, gas-ratios were fine tuned in various experimental trials to obtain a <002> c-axis oriented AlN thin film. Least obtained FWHM from the XRD plots were 0.44°. In Atomic Force Microscopy (AFM) surface roughness of the best quality AlN thin film was 11.1nm. Using Piezo response Force Microscopy (PFM) butterfly loops were constructed and effective piezoelectric co-efficient of 7.28 pm/V was obtained. This co-efficient value is accounting for both the <inline-formula> <tex-math>${mathrm { d}}_{33}$ </tex-math></inline-formula> of the piezoelectric material and the substrate bending for the released membrane structure.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"10-15"},"PeriodicalIF":2.3,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Three-Dimensional Flow Analysis and Humidity Level Evaluation for a FOUP During Open Door Operation Conditions 开门工况下FOUP的三维流动分析与湿度水平评估
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-10-16 DOI: 10.1109/TSM.2025.3622489
Anthony Xavier Andrade;Omid Ali Zargar;Yang-Cheng Shih;Graham Leggett;Shih-Cheng Hu
{"title":"Three-Dimensional Flow Analysis and Humidity Level Evaluation for a FOUP During Open Door Operation Conditions","authors":"Anthony Xavier Andrade;Omid Ali Zargar;Yang-Cheng Shih;Graham Leggett;Shih-Cheng Hu","doi":"10.1109/TSM.2025.3622489","DOIUrl":"https://doi.org/10.1109/TSM.2025.3622489","url":null,"abstract":"Controlling moisture content during silicon wafer fabrication is essential to maintain good product quality, minimize undesired defects, and improve the performance of the manufacturing process. This study investigated the 3D air flow patterns and relative humidity (RH) distribution within a Front Opening Unified Pod (FOUP) used in semiconductor manufacturing. Two purging techniques were evaluated: the diffuser purge method and the diffuser & laminar air curtain (LAC) purge method, to determine their effectiveness in moisture removal when the FOUP door is open under varying flow rates. Computational Fluid Dynamics (CFD) simulations using the Large Eddy Simulation (LES) model were conducted to analyze air flow behavior and RH levels, and the numerical results were validated through experimental measurements using humidity sensors embedded in dummy wafers. The findings demonstrate that the integrated diffuser and LAC purging strategy is a highly effective solution for maintaining low humidity levels in FOUPs, thereby enhancing cleanliness standards critical to semiconductor fabrication.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"46-52"},"PeriodicalIF":2.3,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Addressing Energy and PFAS Chemical Consumption in Semiconductor Manufacturing: Case Study in a University Fab 解决半导体制造中的能源和PFAS化学消耗：以某大学晶圆厂为例
IF 2.3 3区 工程技术
IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-10-14 DOI: 10.1109/TSM.2025.3621131
William P. Shuley;Santosh K. Kurinec
{"title":"Addressing Energy and PFAS Chemical Consumption in Semiconductor Manufacturing: Case Study in a University Fab","authors":"William P. Shuley;Santosh K. Kurinec","doi":"10.1109/TSM.2025.3621131","DOIUrl":"https://doi.org/10.1109/TSM.2025.3621131","url":null,"abstract":"This study involves the tabulation of energy usage for a standard metal-oxide semiconductor field-effect transistor (MOSFET) manufacturing process in a university semiconductor fabrication teaching laboratory. The purpose of the energy audit is to pave the way for further reductions in energy usage and more efficient fabrication processes, to lessen the semiconductor industry’s burden on the global energy supply chain. A prototype photovoltaic system is designed to offset the energy usage of this process providing a vision towards the use of renewables. For the chemical case study, a comparison of reactive ion etching to ion beam etching is done to observe differences in the efficiency and results of the processes and to compare their prospects for widespread use within industry. Reactive ion etching involves the use of harmful per- and polyfluoroalkyl (PFAS) substances. Ion beam etching is another etching technology that is less widespread in large-scale manufacturing but consumes inert gases and does not produce environmental toxins as a byproduct. The study of these two important areas, at an educational level, will be a way for the future of the industry to improve the impact they have on society by re-engineering energy usage and re-thinking chemical usage.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"925-932"},"PeriodicalIF":2.3,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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