IEEE Transactions on Semiconductor Manufacturing最新文献_第10页

Plasma Etching Endpoint Detection in the Presence of Chamber Variations Through Nonlinear Manifold Learning and Density-Based Clustering 通过非线性积分学习和基于密度的聚类在腔室变化的情况下检测等离子刻蚀终点

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-26 DOI: 10.1109/TSM.2024.3434489

Chae Sun Kim;Hae Rang Roh;Yongseok Lee;Taekyoon Park;Chanmin Lee;Jong Min Lee

{"title":"Plasma Etching Endpoint Detection in the Presence of Chamber Variations Through Nonlinear Manifold Learning and Density-Based Clustering","authors":"Chae Sun Kim;Hae Rang Roh;Yongseok Lee;Taekyoon Park;Chanmin Lee;Jong Min Lee","doi":"10.1109/TSM.2024.3434489","DOIUrl":"10.1109/TSM.2024.3434489","url":null,"abstract":"The consistent decrease in the open ratio of wafers has spurred a demand for advanced endpoint detection (EPD) techniques to ensure accurate plasma etching in nonlinear optical emission spectroscopy (OES) data characterized by a low signal-to-noise ratio. Additionally, precise detection of endpoint is hindered by variations between plasma chambers arising from diverse issues. To address these issues, this study proposes a nonlinear manifold learning-based EPD model and a chamber condition identification framework. The EPD model demonstrates the capability to extract endpoint-related latent variables from complex nonlinear OES data. Moreover, the model exhibits the ability to generalize to larger datasets through density-based time series clustering. The chamber condition identification framework not only classifies plasma conditions but also automates the determination of the conditions for incoming new wafers. Evaluation of the proposed approach, conducted using actual OES data from multiple chambers, demonstrated that the EPD model outperformed other models which are based on diverse dimensionality reduction approaches. Furthermore, the chamber condition identification process successfully identified condition variations and accurately determined the plasma condition of new data. Moreover, conducting EPD modeling for separate conditions rather than collectively for diverse conditions demonstrated superior detection results, underscoring the importance of the chamber condition identification process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"553-566"},"PeriodicalIF":2.3,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141778550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Boundless Engineering for Yield to Cope With the Complexity of High-Volume Manufacturing 无止境的产量工程，应对大批量生产的复杂性

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-15 DOI: 10.1109/TSM.2024.3428936

Giyoung Yang;Lay Hoon Loh;Emma Greer;Xiaodong Zhang;Shivendra Pandey;Saramma Varghese;Wee Hong Goh;Jianjun Cheng;Eric Hao Guan;Angelo Pinto

{"title":"Boundless Engineering for Yield to Cope With the Complexity of High-Volume Manufacturing","authors":"Giyoung Yang;Lay Hoon Loh;Emma Greer;Xiaodong Zhang;Shivendra Pandey;Saramma Varghese;Wee Hong Goh;Jianjun Cheng;Eric Hao Guan;Angelo Pinto","doi":"10.1109/TSM.2024.3428936","DOIUrl":"10.1109/TSM.2024.3428936","url":null,"abstract":"This paper describes the art of engineering work that analyzes the causes of yield degradation and contributes yield enhancement through an integrated Engineering for Yield (EFY) framework in the High-Volume Manufacturing (HVM) stage. In this phase, large volumes of wafers are monitored, and defect signatures are clustered to find systematic defects. The yield loss factors are identified through volume diagnosis and the correlation between the sorting yield and the on-chip monitoring sensor is checked. Not only anchoring the production phase analysis but stochastic vulnerabilities which are not expected in the design signoff stage could be discovered through electrical profiling (eProfiling) with Monte-Carlo simulation. This EFY framework improves HVM yield and is applied to the current HVM product portfolio and will continue to be applied to upcoming HVM products. This borderless EFY framework achieves the tangible result of improving the mature yield by >1% by resolving problems that occurred in the HVM stage within a few weeks but also contributes to preventing possible defects for the next HVM products.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"139-145"},"PeriodicalIF":2.3,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141718531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantitative Comparison of Simulation and Experiment Enabling a Lithography Digital Twin 实现光刻数字孪生的模拟与实验定量比较

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-12 DOI: 10.1109/TSM.2024.3427409

Yutong Xie;Benyamin Davaji;Ivan Chakarov;Sandy Wen;Michael Hargrove;David Fried;Peter C. Doerschuk;Amit Lal

{"title":"Quantitative Comparison of Simulation and Experiment Enabling a Lithography Digital Twin","authors":"Yutong Xie;Benyamin Davaji;Ivan Chakarov;Sandy Wen;Michael Hargrove;David Fried;Peter C. Doerschuk;Amit Lal","doi":"10.1109/TSM.2024.3427409","DOIUrl":"10.1109/TSM.2024.3427409","url":null,"abstract":"Digital twins of the semiconductor fabrication process provide means for optimization of the physical layout and nanofabrication process design, studying compatibility between desired structures and a process flow, and a pathway to analyze the root causes of defects for state-of-the-art CMOS and MEMS devices. In this paper, a metric for the geometric differences between structures visualized by CD-SEM images is defined, and a computer-vision-based algorithm is developed to evaluate the metric. One of the major uses of such metrics is to compare experimental and simulated images. For this application, numerical results are presented when the simulator is SEMulator3D®, a physics-based process modeling software system for semiconductor and MEMS devices. Computer vision tools, such as filters, thresholding, and morphology operations, are used to extract geometric features from CD-SEM images and pattern matching and symmetric difference are used to compute the metric. Examples of using the metrics to quantify the geometric similarity between a simulated nanostructure and an experimental CD-SEM image of the fabricated nanostructure are presented. The data consists of eight classes of nanostructures which are defined, fabricated in the cleanroom with 36 combinations of layout parameters, and imaged with a CD-SEM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"546-552"},"PeriodicalIF":2.3,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141614074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111> 半导体单晶-硅生长的结构损失实时自动检测与停止规则

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-07-04 DOI: 10.1109/TSM.2024.3421926

Wheyming Tina Song;Yu-Fan Liao

{"title":"A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111>","authors":"Wheyming Tina Song;Yu-Fan Liao","doi":"10.1109/TSM.2024.3421926","DOIUrl":"10.1109/TSM.2024.3421926","url":null,"abstract":"The occurrence of the “structural-loss” defect during single-crystal silicon growth (SCSG) is a significant issue in semiconductor manufacturing. When structural-loss occurs, it signifies a deviation from the desired quality of single-crystal formation, leading to the need to halt the growth process. Currently, there is a lack of scholarly literature addressing the determination of an optimal stopping time to promptly halt the process upon the occurrence of the defect on-line. Our research makes a substantial contribution by addressing this gap in the SCSG process, specifically focusing on orientations <100> and <111>. The study utilizes advanced AI with YOLO-v7 and innovative approaches. These include precise annotation of crystal misorientation features through a comprehensive definition of structural-loss and novel labeling techniques, identification of optimal hyper-parameters through a robust design, and the implementation of effective stopping rule mechanisms. Significant progress has been achieved in decision-making through the implementation of the stoping time shift to terminate the SCSG process within an average of less than 3 minutes for <100> orientations (with a standard error of 0.3 minutes) and less than 5 minutes for <111> orientations (with a standard error of 0.5 minutes). The promising results indicate that the proposed approaches have the capability to substitute manual inspections, opening up possibilities for new perspectives in this particular field.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"304-315"},"PeriodicalIF":2.3,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141552962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN 基于多路径 DCNN 的混合缺陷模式晶片图识别与分类

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-26 DOI: 10.1109/TSM.2024.3418520

Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu

{"title":"Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN","authors":"Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu","doi":"10.1109/TSM.2024.3418520","DOIUrl":"10.1109/TSM.2024.3418520","url":null,"abstract":"The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"316-328"},"PeriodicalIF":2.3,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy 从 DSH 到扩展-DSH：基于解耦回归策略的芯片级化学机械平坦化 (CMP) 模型升级

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-25 DOI: 10.1109/TSM.2024.3418827

Qian Yue;Chen Lan

{"title":"DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy","authors":"Qian Yue;Chen Lan","doi":"10.1109/TSM.2024.3418827","DOIUrl":"10.1109/TSM.2024.3418827","url":null,"abstract":"Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"329-339"},"PeriodicalIF":2.3,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum 利用整个光学发射光谱对等离子体蚀刻过程中的关键尺寸进行虚拟测量

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-24 DOI: 10.1109/TSM.2024.3416844

Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic

{"title":"Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum","authors":"Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic","doi":"10.1109/TSM.2024.3416844","DOIUrl":"10.1109/TSM.2024.3416844","url":null,"abstract":"This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"363-372"},"PeriodicalIF":2.3,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sustainable Semiconductor Manufacturing: The Role of Lithography 可持续半导体制造：光刻技术的作用

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-19 DOI: 10.1109/TSM.2024.3416830

Emily Gallagher;Lars-Åke Ragnarsson;Cedric Rolin

引用次数: 0

Efficient Dual-Attention-Based Knowledge Distillation Network for Unsupervised Wafer Map Anomaly Detection 基于知识蒸馏网络的高效双注意无监督晶圆图异常检测

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-18 DOI: 10.1109/TSM.2024.3416055

Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani

{"title":"Efficient Dual-Attention-Based Knowledge Distillation Network for Unsupervised Wafer Map Anomaly Detection","authors":"Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani","doi":"10.1109/TSM.2024.3416055","DOIUrl":"10.1109/TSM.2024.3416055","url":null,"abstract":"Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"293-303"},"PeriodicalIF":2.3,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Elimination of Si-C Defect on Wafer Surface in High-Temperature SPM Process Through Nitrogen Purge in 300-mm Single-Wafer Chamber 在高温 SPM 工艺中通过 300 毫米单晶片室中的氮气吹扫消除晶圆表面的 Si-C 缺陷

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-06-18 DOI: 10.1109/TSM.2024.3416079

Rajan Kumar Singh;Alfie Lin;Haley Lin;Max Chen;Yvonne Pan;Nancy Cho;Willy Chen;Jamiet Tung;Walt Hu;Wilson Huang

{"title":"Elimination of Si-C Defect on Wafer Surface in High-Temperature SPM Process Through Nitrogen Purge in 300-mm Single-Wafer Chamber","authors":"Rajan Kumar Singh;Alfie Lin;Haley Lin;Max Chen;Yvonne Pan;Nancy Cho;Willy Chen;Jamiet Tung;Walt Hu;Wilson Huang","doi":"10.1109/TSM.2024.3416079","DOIUrl":"10.1109/TSM.2024.3416079","url":null,"abstract":"During semiconductor manufacturing, the high temperature sulfuric acid peroxide mixture (SPM) and airborne molecule contaminants (AMCs) can result in the formation of defects such as Silicon-carbide (Si-C) on the wafer surface. Furthermore, defects adversely affect device performance, yield, and manufacturing productivity. In this work, a novel approach is proposed by introducing an additional nitrogen (N2) gas purge nozzle inside the single wafer chamber to reduce total volatile organic compounds (t-VOC). Additionally, we provide insights into the mechanism underlying defect formation in SPM which has not been previously explained. In SPM process, defects are formed by AMCs and high temperature. So, various AMCs were investigated in this work. Moreover, the correlation of the number of Si-C defect with temperature and duration of chemical flow was also analyzed. The experimental results demonstrated that defects and t-VOC follow the same concentration trend. Our nitrogen purge method effectively diluted the chamber environment, reducing the adhesion energy between contamination particles and the wafer surface. A suitable N2 purging rate inside the single-wafer chamber facilitated the elimination of around 63% of defects from wafer surface. Hence, this approach can be crucial in minimizing the Si-C defects and improving the chamber environment for high-temperature SPM wet-cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"355-362"},"PeriodicalIF":2.3,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0