IEEE Transactions on Semiconductor Manufacturing最新文献_第10页

Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask 利用锥形氧化硅掩模制造尖端顶点小于 5 纳米的高有序硅纳米锥阵列

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-04 DOI: 10.1109/TSM.2024.3372521

Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui

{"title":"Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask","authors":"Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui","doi":"10.1109/TSM.2024.3372521","DOIUrl":"10.1109/TSM.2024.3372521","url":null,"abstract":"In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"160-165"},"PeriodicalIF":2.7,"publicationDate":"2024-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140037422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Semantic Segmentation for Noisy and Limited Wafer Transmission Electron Microscope Images 噪声和有限晶片透射电子显微镜图像的语义分割

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-03 DOI: 10.1109/TSM.2024.3396423

Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim

{"title":"Semantic Segmentation for Noisy and Limited Wafer Transmission Electron Microscope Images","authors":"Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim","doi":"10.1109/TSM.2024.3396423","DOIUrl":"10.1109/TSM.2024.3396423","url":null,"abstract":"Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"345-354"},"PeriodicalIF":2.3,"publicationDate":"2024-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140831626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Lightweight Chip-Scale Chemical Mechanical Polishing Model Based on Polynomial Network 基于多项式网络的轻量级芯片级化学机械抛光模型

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-26 DOI: 10.1109/TSM.2024.3370175

Ruian Ji;Rong Chen;Lan Chen

引用次数: 0

Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber 二氧化硅沉积室的环保干洗和诊断技术

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-14 DOI: 10.1109/TSM.2024.3365827

Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong

{"title":"Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber","authors":"Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong","doi":"10.1109/TSM.2024.3365827","DOIUrl":"10.1109/TSM.2024.3365827","url":null,"abstract":"Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"207-221"},"PeriodicalIF":2.7,"publicationDate":"2024-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Curvilinear Standard Cell Design for Semiconductor Manufacturing 用于半导体制造的曲线标准单元设计

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-06 DOI: 10.1109/TSM.2024.3362900

Ryoung-Han Kim;Soobin Hwang;Apoorva Oak;Yasser Shirazi;Hsinlan Chang;Kiho Yang;Gioele Mirabelli

{"title":"Curvilinear Standard Cell Design for Semiconductor Manufacturing","authors":"Ryoung-Han Kim;Soobin Hwang;Apoorva Oak;Yasser Shirazi;Hsinlan Chang;Kiho Yang;Gioele Mirabelli","doi":"10.1109/TSM.2024.3362900","DOIUrl":"10.1109/TSM.2024.3362900","url":null,"abstract":"Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"152-159"},"PeriodicalIF":2.7,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139945816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Semiconductor Manufacturing Information for Authors IEEE Transactions on Semiconductor Manufacturing 为作者提供的信息

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-05 DOI: 10.1109/TSM.2023.3334414

引用次数: 0

IEEE Transactions on Semiconductor Manufacturing Publication Information 电气和电子工程师学会半导体制造期刊》出版信息

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-05 DOI: 10.1109/TSM.2023.3334410

引用次数: 0

Call for Papers for IEEE Transactions on Materials for Electron Devices 电气和电子工程师学会《电子器件材料学报》征稿启事

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-05 DOI: 10.1109/TSM.2024.3359520

引用次数: 0

Joint Call for Papers for IEEE Transactions on Semiconductor Manufacturing and IEEE Transactions on Electron Devices: Special Issue on Semiconductor Design for Manufacturing (DFM) IEEE Transactions on Semiconductor Manufacturing》和《IEEE Transactions on Electron Devices》杂志联合征稿：半导体制造设计 (DFM) 特刊

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-05 DOI: 10.1109/TSM.2024.3356972

引用次数: 0

SnS₂ and ZnO Nanocomposite Prepared by Dispersion Method for Photodetector Application 用分散法制备的用于光探测器的 SnS₂ 和 ZnO 纳米复合材料

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2023-12-27 DOI: 10.1109/TSM.2023.3347606

Ajay Kumar Dwivedi;Satyabrata Jit;Shweta Tripathi

引用次数: 0