IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"Current Status of Bulk β-Ga₂O₃ and β-(AlxGa₁-ₓ)₂O₃ Crystal Growth","authors":"Zbigniew Galazka","doi":"10.1109/TSM.2025.3603605","DOIUrl":"https://doi.org/10.1109/TSM.2025.3603605","url":null,"abstract":"<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 and its solid solutions <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-(AlxGa<inline-formula> <tex-math>${}_{text {1-x}}$ </tex-math></inline-formula>)2O3 are considered as potential candidate materials for next generation power devices due to their ultra-wide bandgaps (4.85–5.6 eV) and large breakdown electric field (<inline-formula> <tex-math>$geq 8$ </tex-math></inline-formula> MVcm<inline-formula> <tex-math>${}^{text {-1}}$ </tex-math></inline-formula>). Wafers prepared from bulk crystals constitute a foundation in a device fabrication chain. The present report briefly discusses thermodynamics, challenges in growing bulk crystals from the melt by different methods, which enable at least 2-inch diameter wafers, crystal structural quality, electrical properties, and factors affecting crystal growth costs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"796-802"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11143391","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synthesis of Critical Patterns for Lithography Optimizations Through Machine Learning","authors":"Shilong Zhang;Seohyun Kim;Youngsoo Shin","doi":"10.1109/TSM.2025.3603644","DOIUrl":"https://doi.org/10.1109/TSM.2025.3603644","url":null,"abstract":"Critical patterns are layout patterns that cannot be corrected by standard MB-OPC with enough accuracy. Since they are infrequent, lithography applications targeting critical patterns such as inverse lithography technology (ILT) can suffer from insufficient samples. We propose a method to synthesize critical patterns and their mask patterns. (1) A multilayer perceptron (MLP) model is constructed to predict the probability that the feature vector of a mask pattern, obtained through a mask encoder, is critical. A key is to perform gradient ascent through the MLP network, which has been trained before, to identify some new critical feature vectors. (2) Such vectors are decoded, using a mask decoder, into an image which is refined using a conditional generative adversarial network (cGAN) for final critical mask patterns. (3) A U-Net model is applied to critical mask patterns to discover the critical layout patterns.Experiments are performed for quick ILT through U-Net model. When the synthesized critical mask- and layout-patterns are used to train the U-Net, ILT becomes more accurate and the standard deviation of EPE distribution for ILT outputs is reduced by 36.3%. Lithography modeling is considered for another application of the proposed method. The RMSE of lithography model is reduced by 30.7% when the model is calibrated with synthesized critical layout patterns, compared to base model built with standard test patterns.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"865-875"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adaptive Transfer Learning With Deformable Convolution for Wafer Defect Pattern Recognition","authors":"Jia-Hong Chou;Fu-Kwun Wang;Hsuan-Kai Chen","doi":"10.1109/TSM.2025.3610478","DOIUrl":"https://doi.org/10.1109/TSM.2025.3610478","url":null,"abstract":"The convolutional neural network (CNN) based model has been widely used for wafer map defect pattern recognition. However, it often fails to detect patterns effectively after a few months of deployment due to shifts in data distribution, usually linked to aging inspection tools or recipe changes. To address this issue, researchers have turned to transfer learning techniques. However, most methods require labeled data for the target dataset, which is time-consuming and labor-intensive. Unsupervised domain adaptation (UDA), a transfer learning technique, requires no human labeling and performs better than conventional methods. This study introduces deformable convolutional encoder adversarial discriminator domain adaptation (DC-ADDA), which adapts the deformable convolutional network (DC-Net) as an encoder in the adversarial discriminative domain adaptation method. Using MixedWM38 and synthesized multi-bin wafer bin maps (SWBMs) as source datasets with WM-811K as the target, DC-ADDA outperforms other methods across transfer learning, encoders, and domain adaptation scenarios. The proposed DC-ADDA method achieves an accuracy of 66.46%, a precision of 68.13%, a recall of 69.63%, and an F1-score of 68.41% when applied from MixedWM38 to WM-811K. When applied from SWBMs to WM-811K, it achieves an accuracy of 75.61%, a precision of 75.20%, a recall of 74.81%, and an F1-score of 74.81%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"840-849"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite-Dimensional Observer-Based Control for Time-Delayed Heat Conduction in Silicon Crystal Growth","authors":"Fan Liu;Ding Liu;Pengju Zhang;Hao Pan;Jiayi Ti","doi":"10.1109/TSM.2025.3596860","DOIUrl":"https://doi.org/10.1109/TSM.2025.3596860","url":null,"abstract":"Temperature control is essential for the growth of high-quality, semiconductor-grade silicon single crystals (SSCs) through the Czochralski (Cz) process. However, conventional control systems face significant challenges due to large time delays and limited observation points, which lead to decreased stability and control accuracy. This paper introduces a novel model predictive control (MPC) output feedback controller specifically designed for heat distribution systems that experience simultaneous input and output time delays. The proposed control architecture employs a finite-dimensional observer constructed from measurable outputs. Our approach is developed through four key steps: (i) applying spectral decomposition for modal separation; (ii) designing a Luenberger delayed observer that satisfies linear matrix inequality (LMI) constraints; (iii) deriving reduced-order temperature control equations to capture primary dynamics within a finite-dimensional subspace; and (iv) implementing an MPC output feedback stabilizing control law based on the reduced-order system. The theoretical foundation of the control algorithm is validated through rigorous mathematical derivation. Experimental results demonstrate that the proposed control architecture achieves stable convergence despite the presence of input and output delays, leading to improved crystal quality. This study provides a viable theoretical framework for the growth of SSCs with significant implications for industrial applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"889-900"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Voltage Design Strategies for Gallium Oxide Power Devices","authors":"N. L. Edwards;A. Martinez;J. Evans;J. Mitchell;J. Asher;S. Ghosh;E. Chikoidze;A. P. Tomas;M. Vellvehi;F. Monaghan;J. Burnett;D. Goodwin;O. Guy;C. Fisher;H. Ashraf;C. Colombier;M. Jennings","doi":"10.1109/TSM.2025.3597872","DOIUrl":"https://doi.org/10.1109/TSM.2025.3597872","url":null,"abstract":"This study employs drift-diffusion simulation to investigate key factors influencing the performance of &lt;inline-formula&gt; &lt;tex-math&gt;$beta $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-Ga2O3 FinFETs, demonstrating that enhancement-mode behavior (&lt;inline-formula&gt; &lt;tex-math&gt;$V_{mathrm { th}} gt 0$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) is achievable for &lt;inline-formula&gt; &lt;tex-math&gt;$beta $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-Ga2O3 FinFET using a Fin width &lt;inline-formula&gt; &lt;tex-math&gt;$W_{FIN}leq 0.5~mu $ &lt;/tex-math&gt;&lt;/inline-formula&gt;m and doping concentration &lt;inline-formula&gt; &lt;tex-math&gt;$N_{d}leq 1times 10{^{{16}}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; cm-3. Breakdown voltage and output/transfer characteristics are calculated by using drift-diffusion methodology calibrated by experiments. We found that the metal work function (&lt;inline-formula&gt; &lt;tex-math&gt;$boldsymbol {varnothing }_{m}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;), dielectric constant &lt;inline-formula&gt; &lt;tex-math&gt;$(kappa)$ &lt;/tex-math&gt;&lt;/inline-formula&gt;, and unintentional negative interface charge density (-Qf) at the &lt;inline-formula&gt; &lt;tex-math&gt;$beta $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-Ga2O3/dielectric interface significantly impact Vth, with a high &lt;inline-formula&gt; &lt;tex-math&gt;$varnothing _{m}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; being necessary for enhancement mode (E-mode) operation. To achieve 5kV breakdown, a &lt;inline-formula&gt; &lt;tex-math&gt;$W_{FIN}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; of 200 nm requires a fin thickness &lt;inline-formula&gt; &lt;tex-math&gt;$(T_{FIN})$ &lt;/tex-math&gt;&lt;/inline-formula&gt; of &lt;inline-formula&gt; &lt;tex-math&gt;$0.8~mu $ &lt;/tex-math&gt;&lt;/inline-formula&gt;m, a &lt;inline-formula&gt; &lt;tex-math&gt;$W_{FIN}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; of 400 nm requires &lt;inline-formula&gt; &lt;tex-math&gt;$T_{FIN} {gt }$ &lt;/tex-math&gt;&lt;/inline-formula&gt; &lt;inline-formula&gt; &lt;tex-math&gt;$1.2~mu $ &lt;/tex-math&gt;&lt;/inline-formula&gt;m, and a &lt;inline-formula&gt; &lt;tex-math&gt;$W_{FIN} {gt }$ &lt;/tex-math&gt;&lt;/inline-formula&gt; 600 nm requires &lt;inline-formula&gt; &lt;tex-math&gt;$T_{FIN} {gt }$ &lt;/tex-math&gt;&lt;/inline-formula&gt; &lt;inline-formula&gt; &lt;tex-math&gt;$2~mu $ &lt;/tex-math&gt;&lt;/inline-formula&gt;m. From &lt;inline-formula&gt; &lt;tex-math&gt;$W_{FIN} $ &lt;/tex-math&gt;&lt;/inline-formula&gt;of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e., Vth /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. The presence of -Qf enhances the breakdown voltage by mitigating DIBL-related failure mechanisms and by redistributing the electric potential away from the gate dielectric and deeper into the &lt;inline-formula&gt; &lt;tex-math&gt;$beta $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-Ga2O3 drift region. A controllable and relatively defect-free process was developed for Ga2O3 metal-insulator-semiconductor (MIS) structures, enabling improved interface quality. Capacitance–voltage measurements and progressive annealing studies demonstrate enhanced device stability and reduced hysteresis for the proposed FinFET application. Finally, an optimized &lt;inline-formula&gt; &lt;tex-math&gt;$beta $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-Ga2O3 fin etch process was developed on the KLA SPTS SynapsEtch™ module for Ga2O3 ","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"758-764"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TAFF-YOLO: An Enhanced YOLO Model With Transformer and Attention Feature Fusion for Chip Internal Defect Detection","authors":"Wenxin Niu;Jianqiang Mei;Dawei Zhang;Yue Li;Fan Jia;Weixiang Du","doi":"10.1109/TSM.2025.3597147","DOIUrl":"https://doi.org/10.1109/TSM.2025.3597147","url":null,"abstract":"Accurate and efficient detection of internal defects in chips is crucial for ensuring the reliability and yield of electronic products. However, conventional object detection models often struggle to identify such defects in ultrasonic images due to their extremely small size and low contrast. To overcome these challenges, a novel detection framework that combines image processing with a Transformer-based Attention Feature Fusion YOLO model (TAFF-YOLO) is proposed in this paper. The framework first employs image processing methods to extract individual chip images and then applies a handcrafted feature generation algorithm for data augmentation to mitigate overfitting. Subsequently, the TAFF-YOLO model is introduced for precise defect localization. Specifically, a Deformable Attention Background Suppression Module (DABSM) is integrated to enhance global contextual information and the receptive field for detecting small objects. Additionally, the feature fusion network (neck) is augmented with a ResBlock and Convolutional Block Attention Module (ResCBAM) to focus the model effectively on critical defect regions while suppressing irrelevant background noise. A Smooth Intersection over Union (SIoU) loss function further stabilizes the training and enhances localization accuracy. Experimental results from two private datasets and one public dataset demonstrate that the proposed method achieves an average precision of 90.9%, with a compact model size of 2.6 million parameters and an inference speed of 167.3 FPS, effectively balancing detection accuracy, model complexity, and processing speed. This indicates significant promise for real-time industrial chip inspection applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"876-888"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New Patterned Wafer Shape Metrology Technique for In-Plane Distortion Predictions","authors":"Jan O. Gaudestad;Jose M. Rodriguez-Ramos;Jose G. Marichal-Hernandez","doi":"10.1109/TSM.2025.3601522","DOIUrl":"https://doi.org/10.1109/TSM.2025.3601522","url":null,"abstract":"In semiconductor manufacturing, achieving precise overlay alignment between successive lithography layers is critical. Current methods face challenges due to non-lithographic process-induced wafer shape changes that cause in-plane distortions (IPD). This study presents Wave Front Phase Imaging (WFPI), a new technique that measures wafer shape by analyzing the intensity of reflected light without requiring interference. WFPI’s capability to produce high-resolution shape maps allows for accurate prediction of IPD. WFPI utilizes two intensity images at distinct optical distances to construct phase maps indicative of wafer topography. Our evaluation on test wafers reveals that WFPI can accurately predict IPD, matching lithography scanner outputs. The paper also shows that WFPI can acquire the wafer shape on a fully patterned 300mm silicon wafer on both frontside and backside. This technique shows the potential to significantly improve overlay accuracy, supporting advanced semiconductor manufacturing processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"818-825"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11133659","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-Scale Adaptive Inspection Framework for Voids in MOSFETs","authors":"Huankang Tang;Weibin Li;Jianghua Nie;Wenzhao Liang;Nian Cai;Jian Chen","doi":"10.1109/TSM.2025.3604212","DOIUrl":"https://doi.org/10.1109/TSM.2025.3604212","url":null,"abstract":"During reflow soldering, Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) are prone to internal voids. A high void ratio for a MOSFET significantly affects its electrical performance to further decrease the reliability and lifespan of the electronic device. In this article, a multi-scale adaptive inspection framework is proposed to inspect internal voids in MOSFETs through X-ray imaging. First, a location-aware vertex detection scheme is utilized to detect the transistor region possibly involving the voids, which makes full advantages of the neighborhood grayscale distributions of the transistor region vertices. Then, after the detected transistor region is preprocessed and divided into several patches, coarse-to-fine void inspection is performed on the patches for void inspection. Specifically, a multi-scale scheme is proposed for coarse void inspection to identify whether the patches involve the potential voids, in which an identification function is defined by integrating the constructed multi-scale radial decaying weight matrix and a fitting metric to characterize the patches. An adaptive thresholding scheme is proposed to finely inspect the voids in the MOSFETs, in which the segmentation threshold model is constructed based on grayscale distributions of the MOSFET X-ray images. Finally, the void ratio is calculated according to the detected transistor and the voids. Experimental results indicate that the proposed framework achieves better inspection performance for voids in MOSFETs than some existing methods at the speed of 0.812s per MOSFET, with an average Dice of 0.8852, an Accuracy of 97.11%, and an F1-score of 0.9819.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"826-839"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterizing Capacitor Top Plate Bias for More Accurate Electromagnetic Simulations","authors":"Peter J. Zampardi;Quinn Davenport;Leonard Hayden","doi":"10.1109/TSM.2025.3600905","DOIUrl":"https://doi.org/10.1109/TSM.2025.3600905","url":null,"abstract":"As frequencies increase, the use of smaller value metal-insulator-metal (MIM) capacitors increases. For small capacitors, errors due to the bias (as fabricated to as drawn difference) of the top plate can cause significant errors. This bias is not correctly monitored with resistance based <inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>W (RLWB) monitors and can be made worse if the resistive based RLWB is used. We present a simple capacitive based technique that uses only two test capacitors to determine the value of the capacitive linewidth bias (CLWB) that is more appropriate for use electromagnetic (EM) simulation and provides consistency with typical MIM compact models.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"770-774"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New Quality Index to Improve Overlay Measurement Accuracy Based on Moiré Marks: Method for Quantifying Moiré Pattern Quality Using the Signal Shape Index","authors":"Hyunchul Lee;Hyunjin Chang;Hosung Woo;Wongyu Lee","doi":"10.1109/TSM.2025.3608946","DOIUrl":"https://doi.org/10.1109/TSM.2025.3608946","url":null,"abstract":"As semiconductor integrated circuits become increasingly miniaturized, overlay metrology has garnered significant attention. Moiré marks offer superior accuracy and robustness compared to conventional grating marks; however, their sensitivity to various optical system parameters can affect measurement precision. This study presents a novel quality index, termed the signal shape index, to quantitatively assess the quality of Moiré marks, which are a crucial factor in enhancing the reliability of overlay metrology. Current quality indices primarily focus on signal strength, consistency, and asymmetry; however, they inadequately capture vital information regarding the shape of Moiré patterns. To address this limitation, the comprehensive index quantifies the shape of Moiré patterns, providing a more effective evaluation of their quality. This shape-based quality index is compared with the established modulation transfer function index. The new index more accurately reflects the characteristics of Moiré patterns, thereby facilitating the optimization of optical system parameters. Implementing this novel quality index is expected to significantly improve the accuracy of Moiré mark-based overlay metrology, contributing to the stabilization and efficiency of semiconductor manufacturing processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"803-811"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}