IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"Model-Based OPC With Adaptive PID Control Through Reinforcement Learning","authors":"Taeyoung Kim;Shilong Zhang;Youngsoo Shin","doi":"10.1109/TSM.2025.3528735","DOIUrl":"https://doi.org/10.1109/TSM.2025.3528735","url":null,"abstract":"Model-based optical proximity correction (MB- OPC) relies on a feedback loop, in which correction result, measured as edge placement error (EPE), is used for decision of next correction. A proportional-integral-derivative (PID) control is a popular mechanism employed for such feedback loop, but current MB-OPC usually relies only on P control. This is because there is no systematic way to customize P, I, and D coefficients for different layouts in different OPC iterations.We apply reinforcement learning (RL) to construct the trained actor that adaptively yields PID coefficients within the correction loop. The RL model consists of an actor and a critic. We perform supervised pre-training to quickly set the initial weights of RL model, with the actor mimicking standard MB-OPC. Subsequently, the critic is trained to predict accurate Q-value, the cumulative reward from OPC correction. The actor is then trained to maximize this Q-value. Experiments are performed with aggressive target maximum EPE values. The proposed OPC for test layouts requires 5 to 7 iterations, while standard MB-OPC (with constant coefficient-based control) completes in 20 to 28 iterations. This reduces OPC runtime to about 1/2.7 on average. In addition, maximum EPE is also reduced by about 24%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"48-56"},"PeriodicalIF":2.3,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advancing Condition-Based Maintenance in the Semiconductor Industry: Innovations, Challenges and Future Directions for Predictive Maintenance","authors":"Jingyu Park;Byeongsun Yoo;Song Yi Baek;Chulkyu Youn;Sundoo Kim;Dowan Kim;Sangho Roh;Se Jun Park;Jaehyun Kim;Changsoo Lee;Chulhwan Choi","doi":"10.1109/TSM.2025.3530964","DOIUrl":"https://doi.org/10.1109/TSM.2025.3530964","url":null,"abstract":"This study focuses on the criticality of failure detection and condition-based maintenance (CBM) within the semiconductor industry, employing Fault Detection and Classification (FDC) systems and Machine Learning (ML) techniques for equipment log analysis to anticipate equipment conditions and timely maintenance. Initiatives emphasize the cultivation of data engineering experts, enhancing depth in data analytics and equipment monitoring. Moreover, the imperative to advance the field lies in the development of innovative sensor technologies, a task that necessitates close collaboration with equipment manufacturers. This strategic partnership is indispensable for augmenting the precision and breadth of data acquisition. It ultimately enables more sophisticated analytics, thereby facilitating the creation of advanced predictive failure models through enhanced data capture and analysis. This paper illustrates the semiconductor sector’s competitive adoption of diverse strategies and technologies for maintenance innovation, aiming to bolster industry productivity, equipment reliability, and sustainability. Such endeavors are pivotal for outlining the future trajectory of manufacturing and ensuring sustainable growth within the industry.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"96-105"},"PeriodicalIF":2.3,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Controlling Speckle Contrast Using Existing Lithographic Scanner Knobs to Explore the Impact on Line Width Roughness","authors":"Heehong Lee;Hyosung Lee;Dirk van Leuken;Hyungju Rah;Wout Keijers;Seunghui Seon;Younghwi Kim;Ijen van Mil;Yongchan Kim;Byungdeog Choi","doi":"10.1109/TSM.2025.3530971","DOIUrl":"https://doi.org/10.1109/TSM.2025.3530971","url":null,"abstract":"Local critical dimension uniformity (LCDU) or line width roughness (LWR) is increasingly important in argon fluoride (ArF) immersion lithography systems (scanners) due to its growing contribution to edge placement error (EPE), an important parameter for circuit designers. A significant scanner contributor to LCDU is speckle, a light interference pattern that arises due to random coherent wavelet interference. In lithography systems (scanners), speckle will result in non-uniform dose delivery to the mask, causing local CD variations of the patterns imaged in the resist. This is an unwanted effect that potentially results in defects and should thus be controlled. In this work, existing lithographic scanner knobs are used to vary speckle contrast to showcase what product performance gain it can bring on LWR. This is achieved by slowing down the exposure speed, decreasing speckle contrast due to an increased number of pulses that fit in the exposure slit. However, this simultaneously brings scanner dynamics improvement that enhances imaging contrast which in turn also improves LWR. In order to decouple the dynamics and speckle improvement, additional experiments are required. This is done by restoring the speckle contrast for the slowed down exposures by adjusting the pulsed laser repetition rate. In the end, this series of experiments leads to a powerful framework to evaluate solely the speckle gain to product performance. In this work, the method is used to predict the LWR performance gain of the new ASML pulse stretcher which is designed to improve speckle contrast. Next to that, simulations are performed which accurately forecast the experimental results, demonstrating the robustness of the proposed framework. This work not only offers insights into optimizing the lithographic processes for improved product performance but also lays the groundwork for further exploration into scanner control strategies to minimize LWR and enhance yield in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"29-35"},"PeriodicalIF":2.3,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10844692","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing Current Gain in Polysilicon Emitter Bipolar Transistors Through Emitter-Base Interface Engineering","authors":"Adukkadukkam Dineshan;Jane Chow;Hiew Hock Hing","doi":"10.1109/TSM.2025.3529436","DOIUrl":"https://doi.org/10.1109/TSM.2025.3529436","url":null,"abstract":"Polysilicon is extensively employed as a material for emitters in vertical bipolar junction transistors (BJTs) to achieve high current gain (beta). To enhance the electrical properties of polysilicon emitter BJTs, meticulous engineering of the interface between the emitter polysilicon and the base is crucial. This paper begins by elucidating the sources and implications of variations in interface oxide thickness observed in polysilicon emitter PNP transistors. The deposition of the polysilicon emitter is performed using the low-pressure chemical vapor deposition (LPCVD) furnace process. The formation of native oxide during the LPCVD furnace loading results in significant discrepancies in current gain across different positions within the furnace boat. To understand the underlying mechanisms, we employ thickness measurements through ellipsometry, transmission electron microscopy (TEM) grain analysis, and electrical characterization. To mitigate these variations, several experimental approaches have been pursued. This paper reports that the application of a thin layer of chemical oxide at the interface—achieved through an HF-first RCA clean prior to polysilicon deposition—can establish a controllable, repeatable, and uniform layer of interface oxide. This consistent chemical oxide effectively passivates the silicon surface, leading to stable and uniform electrical performance across all furnace boat positions, thus eliminating variations attributed to furnace loading and waiting times. The proposed solution significantly improves furnace utilization, yield, process capability indices (Cp and Cpk), while also reducing associated costs. Furthermore, this paper introduces an innovative method to modify the emitter-base interface utilizing plasma surface treatment, aimed at enhancing the average current gain performance across all boat positions without compromising breakdown and leakage characteristics. The plasma treatment, which incorporates the application of bias power, induces surface roughness that inhibits the epitaxial realignment of the emitter polysilicon, thereby improving current gain.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"375-382"},"PeriodicalIF":2.3,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of Porous Cu–Sn Microbumps for Low-Temperature Cu–Cu Bonding","authors":"Zilin Wang;Yunfan Shi;Qingchao Zhang;Yikang Zhou;Qian Wang;Zheyao Wang","doi":"10.1109/TSM.2025.3529683","DOIUrl":"https://doi.org/10.1109/TSM.2025.3529683","url":null,"abstract":"Cu-Cu thermocompression bonding (TCB) is widely used in 3D integration due to its excellent electrical performance, high bonding strength, and good reliability. However, TCB needs high temperature, high pressure, and complicated chemical-mechanical-planarization (CMP). We have developed a low temperature, CMP-free Cu-Cu bonding method using porous Cu-Sn microbumps. In this paper, we further report the detailed fabrication processes and the formation principles of the porous Cu-Sn bumps, as well as the characterization results of the bonded structures. A pretreatment method is developed using sequential thermal reflow and redox treatment in a gas mixture of oxygen and formic acid to form porous Cu-Sn bumps. The gas content, temperature, and duration of the pretreatment are optimized. An array of <inline-formula> <tex-math>$1000times 800$ </tex-math></inline-formula> porous Cu-Sn bumps has been fabricated, and CMP-free Cu-Cu bonding has been achieved using Cu-Sn bumps at 250°C, 10 MPa, and 30 min. The bonding strength, the resistance, and the thermal reliability are evaluated.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"343-351"},"PeriodicalIF":2.3,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ML-Guided Curvilinear OPC: Fast, Accurate, and Manufacturable Curve Correction","authors":"Seohyun Kim;Shilong Zhang;Youngsoo Shin","doi":"10.1109/TSM.2025.3527514","DOIUrl":"https://doi.org/10.1109/TSM.2025.3527514","url":null,"abstract":"In curvilinear optical proximity correction (OPC), each segment is modeled by a cubic Bézier curve, defined by two endpoints and two intermediate points. Iterative correction of these points is not trivial, and a simple heuristic (Chen et al., 2024) has been used but is not effective. A vertex placement error (VPE) is first introduced to replace edge placement error (EPE) in standard Manhattan OPC. Two machine learning models are applied for accurate curve correction. (1) An MLP is used to locate the new endpoints, while VPE from the previous iteration and a few PFT signals representing local light intensity are provided as inputs. (2) A VPE predictor, constructed with GCNs, is designed to output average (or maximum) VPE over a given layout clip. Once trained, it is used to identify intermediate points after new endpoints are fixed by MLP; this is done through gradient descent optimization such that VPE is minimized and curvature constraints are respected as much as possible. Experimental results demonstrate that the proposed curvilinear OPC reduces OPC iterations from 8 to 5 when average VPE is considered as a target or from 14 to 5 when maximum VPE is a target, with a final VPE reduction of about 5 to 6%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"19-28"},"PeriodicalIF":2.3,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated Electrochemical Technology for Efficient Metal Recovery in Semiconductor Wastewater","authors":"Cameron A. Lippert;James R. Landon;Jason Keleher;Alan Rassoolkhani","doi":"10.1109/TSM.2025.3527310","DOIUrl":"https://doi.org/10.1109/TSM.2025.3527310","url":null,"abstract":"In this paper, we investigate the potential of a High Efficiency Selective Electrochemical Cell (HESEC) to recover copper from a variety of semiconductor wastewater streams while also achieving EPA discharge compliance. The copper chemical-mechanical planarization (CuCMP), wet etch, and electroplating processes produce significant levels of copper laden wastewaters with complex matrices that make recovery of the copper difficult. Based on our experimental results, the HESEC provides insight into how novel electrochemical cell designs can be used to achieve selective copper removal and recovery from different wastewater streams and open new possibilities for economical point source treatment and implementation of sustainable practices.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"413-419"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Geometry-Based Curvilinear Mask Process Correction for Enhanced Pattern Fidelity, Contrast, and Manufacturability","authors":"Chun-Hung Liu;Ze-An Ding","doi":"10.1109/TSM.2024.3521368","DOIUrl":"https://doi.org/10.1109/TSM.2024.3521368","url":null,"abstract":"Curvilinear (CL) mask patterns, essential for extreme ultraviolet lithography in advanced semiconductor manufacturing, suffer from degraded fidelity and contrast due to complex pattern environments and severe proximity effects, necessitating CL mask process correction (CL-MPC). However, conventional shape-based CL-MPC methods cannot enhance image contrast because of their inability to adjust dose levels, while dose-based methods require extensive computational time and are incompatible with electron beam writers lacking dose adjustment capabilities. Therefore, this study proposes a two-layer geometry-based CL-MPC method integrating pattern fidelity and image contrast co-optimization with pattern manufacturability enhancement. It employs two overlapping patterns, each of which adjusts the geometry without modifying the dose. A skeleton-based approach creates CL pattern fragments, and dual proportional-integral–derivative controllers improve the pattern fidelity more effectively by classifying the energy slope of target points. For image contrast improvement, a feedback mechanism replaces unsatisfactory parameters with optimized values by minimizing the reciprocal of the energy slope of target points. The pattern manufacturability enhancement further improves mask fabrication by smoothing edge corners and optimizing pattern angles. The proposed method significantly improves pattern fidelity, image contrast, correction runtime efficiency, and manufacturability, making corrected patterns compatible with all electron-beam writers and presenting a promising solution for CL-MPC limitations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"36-47"},"PeriodicalIF":2.3,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Mechanism of an Etching-Back to Reduce the Density of Cone Defect in STI During the Manufacturing","authors":"Chih-Cherng Liao;Jian-Hsing Lee;Yu-Jui Chang;Kai-Chuan Kan;Ching-Kuei Shih;Ya-Huei Kuo;Pei-Chen Tsai;Chien-Hsien Song;Ke-Horng Chen","doi":"10.1109/TSM.2024.3519780","DOIUrl":"https://doi.org/10.1109/TSM.2024.3519780","url":null,"abstract":"The formation of cone defects is a side effect of the shallow trench isolation (STI) etching process, caused by the redeposition of residue from silicon nitride, silicon dioxide, or byproducts from the etching process. This study aims to explain the mechanism responsible for these defects during STI etching. The utilization of this model can enhance the design for manufacturability by streamlining the manufacturing process, reducing susceptibility to defects and process variations, and ultimately improving the reliability and manufacturability of production.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"134-138"},"PeriodicalIF":2.3,"publicationDate":"2024-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Study of the Impact of LWR on Device Performance in VLSI Technology","authors":"Yaoting Wang;Yongyu Wu;Dawei Gao;Kai Xu","doi":"10.1109/TSM.2024.3511918","DOIUrl":"https://doi.org/10.1109/TSM.2024.3511918","url":null,"abstract":"Line Width Roughness (LWR) has emerged as a pivotal challenge that the semiconductor manufacturing industry must confront. This study provides experimental data to elucidate the mechanism by which LWR affects device performance in different processing layers. First, Hard Mask (HM) technology was used to reduce LWR of Active Area (AA) and polysilicon gate by 0.97 nm and 0.62 nm, respectively, resulting in a 21.79% and 55.82% decrease in threshold voltage variability. With the application of HM technology in AA layer processing, the device performance of NMOS and PMOS was also improved by 19.58% and 12.54%, respectively. This improvement can be attributed to the mitigation of carrier scattering induced by LWR. Moreover, HM technology was also conducted in polysilicon gate process which can reduce LWR effectively, thereby enhancing device stability, decreasing the drain-induced barrier lowering factor by approximately 10%, and suppressing gate-induced drain leakage current and overlap capacitance. Consequently, this process contributes to the alleviation of short channel effects. Our research provides experimental groundwork for diminishing LWR, supplies guidelines for understanding the distinct mechanisms of LWR, and offers effective route toward enhancing device performance, and controlling fluctuations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"12-18"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}