IEEE Transactions on Semiconductor Manufacturing最新文献_第8页

Artificial Intelligence–Based Evaluation System With Domain Adaptation for Ultrathin Wafer Detaping 基于领域自适应的超薄晶圆剥离人工智能评价系统

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-07 DOI: 10.1109/TSM.2025.3630127

Gene Eu Jan;Hsin-Lung Wu;Jia-Xi Zhao;Bor-Shing Lin

{"title":"Artificial Intelligence–Based Evaluation System With Domain Adaptation for Ultrathin Wafer Detaping","authors":"Gene Eu Jan;Hsin-Lung Wu;Jia-Xi Zhao;Bor-Shing Lin","doi":"10.1109/TSM.2025.3630127","DOIUrl":"https://doi.org/10.1109/TSM.2025.3630127","url":null,"abstract":"As high-density packaging and low power consumption are prioritized in semiconductor production, ultrathin wafer processing has become vital. However, the fragile nature of these wafers often leads to damage during manual detaping, a process that is time-consuming, labor-intensive, and subjective. To address this, we developed an automated evaluation system integrating You Only Look Once version 8 (YOLOv8) with domain adaptation for robust performance under environmental variations. Through real-time image analysis, the system tracks detaping motion and quantifies operational stability using a finite state machine to calculate operation time. Experimental results under supervised learning showed average motion detection recall and precision of 99.06% and 98.33%, with a mean absolute error (MAE) of 0.17 s. Crucially, the proposed semi-supervised domain adaptive framework mitigated data distribution differences; in one experiment, mAP50 improved by 72.62% from baseline. For motion detection across two domain adaptation experiments, the system maintained high performance, with average precision and recall of 95.4% and 93.5% and an MAE of 0.275 s. This system provides an effective, automated evaluation of manual detaping, demonstrating the value of domain adaptation-based object detection in industrial applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"39 1","pages":"16-27"},"PeriodicalIF":2.3,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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2025 Index IEEE Transactions on Semiconductor Manufacturing 半导体制造学报

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-04 DOI: 10.1109/TSM.2025.3628524

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A Hybrid Electron Beam Lithography Approach to Wafer Scale Up of 150 mm InP Ridge Lasers 150mm InP脊激光器晶圆放大的混合电子束光刻方法

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-08-22 DOI: 10.1109/TSM.2025.3601735

Tomas Peach;Ben Salmond;Tyrone Jones;Elizabeth Beaumont;Stuart Thomas;Angela Sobiesierski;Samuel Shutts

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Macro and Micro-Scale Non-Contact Imaging of Electrically Active Extended Defects in 4H-SiC Merged PiN Schottky Diode Devices 4H-SiC合并PiN肖特基二极管中电活性扩展缺陷的宏、微尺度非接触成像

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-09-26 DOI: 10.1109/TSM.2025.3614854

Firas Faisal;Nils Steller;Robin Karhu;Birgit Kallinger;Gennadi Polisski;Marshall Wilson;Alexandre Savtchouk;Liliana Gutierrez;Carlos Almeida;Cordero Soto;Bradley Wilson;Dmitriy Marinskiy;Adam Wincukiewicz;Jacek Lagowski

{"title":"Macro and Micro-Scale Non-Contact Imaging of Electrically Active Extended Defects in 4H-SiC Merged PiN Schottky Diode Devices","authors":"Firas Faisal;Nils Steller;Robin Karhu;Birgit Kallinger;Gennadi Polisski;Marshall Wilson;Alexandre Savtchouk;Liliana Gutierrez;Carlos Almeida;Cordero Soto;Bradley Wilson;Dmitriy Marinskiy;Adam Wincukiewicz;Jacek Lagowski","doi":"10.1109/TSM.2025.3614854","DOIUrl":"https://doi.org/10.1109/TSM.2025.3614854","url":null,"abstract":"This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD (Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky (MPS) diode manufacturing process and is compared to final wafer-level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on in-die depletion voltage values, allowing for a direct die to die comparison with standard EOL (End of the Line) electrical device testing. The QUAD mapping flow plan includes initial epi-wafers, the EOL wafers with measurement on metalized MPS dies, and the wafers after stripping off the metal. Micro-scale, <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>QUAD depletion voltage maps resolving individual dies gives further insight into the nature of the device failures. Novel results show processing induced failures associated with defective electrical isolation of diodes. The unique yield-killing effects of clusters of stacking fault triangular defects are evidenced by a catastrophic breakdown voltage collapse and QUAD depletion voltage collapse in clusters of failed dies near the wafer edges. A strong correlation between the inline QUAD bin map results and final failed device maps highlights the potential of QUAD as a practical and powerful inline tool. This technique, achieving a 94% capture of failing MPS dies, offers a complementary approach to UVPL defect imaging, identifying electrical killer-defects and enhancing the yield estimations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"744-749"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Semiconductor Manufacturing Publication Information IEEE半导体制造学报

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-10-31 DOI: 10.1109/TSM.2025.3622877

引用次数: 0

Use of E-Beam Lithography to Optimize Lithography Patterning on SiC Wafers 利用电子束光刻优化SiC晶圆上的光刻图案

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-09-09 DOI: 10.1109/TSM.2025.3604717

K. Chen;Z. Feng;S. Williams;R. Van Art;Z. Chen;T. A. Prescop;A. C. Ceballos;K. P. MacWilliams

{"title":"Use of E-Beam Lithography to Optimize Lithography Patterning on SiC Wafers","authors":"K. Chen;Z. Feng;S. Williams;R. Van Art;Z. Chen;T. A. Prescop;A. C. Ceballos;K. P. MacWilliams","doi":"10.1109/TSM.2025.3604717","DOIUrl":"https://doi.org/10.1109/TSM.2025.3604717","url":null,"abstract":"Silicon carbide (SiC) is a wide bandgap semiconductor material used to manufacture high-voltage and high-temperature operating devices. As SiC technology continues to advance, the density of devices across a wafer increases as transistors become smaller. On commonly used 6-inch SiC wafers, the wafers are subject to wafer bowing due to the physical hardness of the material. Optical-based lithography faces several critical challenges when applied to the fabrication of SiC and other wide bandgap semiconductors, particularly in advanced device architectures like FinFETs and T-gate structures. A major limitation is the shallow depth of focus inherent in optical lithography systems. Because SiC devices often involve non-planar topographies—due to deep etching, thick epitaxial layers, or trench structures—the limited depth of focus can lead to pattern defocusing and critical dimension (CD) variation across uneven surfaces. This is especially problematic when trying to define narrow fins or ultra-short gate lengths, where nanometer-level precision is essential for device performance and yield. Further, implementing conventional photolithography can lead to resolution inconsistencies across the wafer and significantly reduce yield. Cross-wafer yield is a challenge that can be addressed with e-beam lithography (EBL). E-beam direct-write lithography demonstrates superior fidelity of nanoscale features due to its great depth of focus over challenging topography on 6-inch and greater diameter SiC wafers. All the while, the specific multicolumn e-beam lithography (MEBL) system implemented herein overcomes throughput challenges historically hampering EBL, making it a production-worthy lithography system for compound semiconductors.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"765-769"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Self-Powered Wireless Sensing Circuitry for On-Wafer In-Situ EUV Detection 一种用于片上原位EUV检测的自供电无线传感电路

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-09-01 DOI: 10.1109/TSM.2025.3604789

Wei Chang;Kuan-Ting Yeh;Burn Jeng Lin;Pin-Jiun Wu;Jenny Yi-Chun Liu;Jiaw-Ren Shih;Chrong Jung Lin;Ya-Chin King

引用次数: 0

Optimized Process Integration of Photolithography With Dose Compensation for Enhanced Resistance Uniformity of Sputtered TaN Thin Film Resistors 提高溅射TaN薄膜电阻均匀性的剂量补偿光刻工艺优化集成

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-08-19 DOI: 10.1109/TSM.2025.3600379

Stephanie Y. Chang;Tom Brown;Rainier Lee;Nercy Ebrahimi

{"title":"Optimized Process Integration of Photolithography With Dose Compensation for Enhanced Resistance Uniformity of Sputtered TaN Thin Film Resistors","authors":"Stephanie Y. Chang;Tom Brown;Rainier Lee;Nercy Ebrahimi","doi":"10.1109/TSM.2025.3600379","DOIUrl":"https://doi.org/10.1109/TSM.2025.3600379","url":null,"abstract":"This paper discusses the implementation of enhanced process controls derived from design of experiments (DOE) that were performed in the optimization of the device fabrication’s resistor layer (RL) process flow to achieve TaN thin film resistors (TFR) with high resistance uniformity. Fine-tuned stepper recipes with optimized exposure dose compensation ratios significantly minimized the resistance variation attributed to the RL photolithography and reactive sputter deposition processes. Experimental studies demonstrated how critical dimensions (CD) are influenced by the chemical amplification of the photoresist, variations in hot plate processing conditions and lid exhaust, wafer’s thermal history during the post-exposure bake (PEB), and coupling time (CT) between process-sensitive steps. These learnings were used to develop a robust process monitoring scheme with a reduced turnaround time by fourfold for inline electrical characterization of process control monitor (PCM) for TaN-related parameters in addition to automated fault detection and classification (FDC) capabilities. This significantly reduced mean-time-to-detection (MTTD) of process anomalies, tightened statistical process control (SPC), improved process capabilities (Cpk), decreased cycle time for enhanced fab productivity, and achieved record-high RL probe yields and final test yields.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"775-782"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Grain Morphology Effects on Void Formation and Electromigration-Induced Failure in Copper Interconnects 晶粒形貌对铜互连中空穴形成和电迁移失效的影响

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-07-28 DOI: 10.1109/TSM.2025.3593054

Han Jiang;Susu Li;Zhenchao Li;Leyin Zhang;Yaohua Xu;Saranarayanan Ramachandran;Shuibao Liang

{"title":"Grain Morphology Effects on Void Formation and Electromigration-Induced Failure in Copper Interconnects","authors":"Han Jiang;Susu Li;Zhenchao Li;Leyin Zhang;Yaohua Xu;Saranarayanan Ramachandran;Shuibao Liang","doi":"10.1109/TSM.2025.3593054","DOIUrl":"https://doi.org/10.1109/TSM.2025.3593054","url":null,"abstract":"Electromigration, driven by increasing current densities in scaled integrated circuits, poses a serious reliability challenge in semiconductor manufacturing, often culminating in void formation and interconnect failure. As interconnect dimensions shrink to the nanoscale, the influence of microstructural features and grain morphology on interconnect reliability and degradation mechanisms becomes increasingly significant. In this work, we develop a physics-based phase field model to investigate the void formation and evolution in copper interconnects subjected to electromigration. Our simulations closely align with experimental trends, revealing that voids predominantly emerge at or initiate from the cathode end, with their evolution strongly influenced by grain morphology. In the surface diffusion-limited scenario (SDLS), grain boundaries significantly promote void formation, resulting in increased void sizes. Under the grain boundary diffusion-limited scenario (GBDLS), void nucleation in bamboo structure (BS) and polycrystalline structure (PS) interconnects occurs relatively early, often initiating near the interface between the copper and the capping layer. The voltage distribution exhibits noticeable inhomogeneity, with high electric field intensities localized at grain boundaries and void surfaces. The electromigration-induced mass flux predominantly flows from the bottom right toward the left. Additionally, an increased number of copper grains leads to larger voids, with a more pronounced effect in the SDLS. Furthermore, electromigration-induced void growth progressively reduces electrical conductivity. These findings elucidate the complex interplay between grain morphology, electromigration-driven void formation, and electrical performance degradation in copper interconnects, and are anticipated to offer valuable insights into microstructure-dependent failure mechanisms while supporting process optimization in advanced interconnect fabrication.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"850-857"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148463874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Vertical GaN Trench MOSFETs With HfO₂/Al₂O₃ Layered Gate Dielectric HfO₂/Al₂O₃层状栅极电介质的垂直GaN沟槽mosfet

IF 2.5 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-11-01 Epub Date: 2025-08-08 DOI: 10.1109/TSM.2025.3596980

E. Brusaterra;E. Bahat Treidel;P. Paul;M. Damian Cuallo;F. Brunner;I. Ostermay;O. Hilt

{"title":"Vertical GaN Trench MOSFETs With HfO₂/Al₂O₃ Layered Gate Dielectric","authors":"E. Brusaterra;E. Bahat Treidel;P. Paul;M. Damian Cuallo;F. Brunner;I. Ostermay;O. Hilt","doi":"10.1109/TSM.2025.3596980","DOIUrl":"https://doi.org/10.1109/TSM.2025.3596980","url":null,"abstract":"In this work, vertical GaN trench MOSFETs have been fabricated by implementing hafnium oxide (HfO2) layered with aluminum oxide (Al2O3) as gate dielectric to improve the device performance when compared to devices using Al2O3 only. The transistors with HfO2/Al2O3 layered gate dielectrics show up to <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> higher forward current, <inline-formula> <tex-math>$5times $ </tex-math></inline-formula> higher gate breakdown voltage and substantially reduced threshold voltage shift induced by gate forward voltage stress when compared to transistors using Al2O3 layered gate dielectric. Higher channel mobility (<inline-formula> <tex-math>$sim ~11.1$ </tex-math></inline-formula> cm2/Vs) and reduced<sc>on</small>-state resistance (<inline-formula> <tex-math>$3.1~pm ~0$ </tex-math></inline-formula>.6 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula> cm2) were also observed as a result of the improved gate module. Post-deposition temperature stability of pure HfO2 layers as well as layered dielectrics combining both HfO2 and Al2O3 is tested combined with plasma pre-deposition surface treatment of gallium nitride to reduce interface trap density. Metal-insulator-semiconductor capacitors have been used as test structures for quick electrical characterization. Pure HfO2 layers show stability up to 500 ° C and present a relative dielectric constant of 17.5 and breakdown electric field of 6.5 MV/cm. The layered dielectric features a lower relative dielectric constant of 12.8 while keeping the same temperature stability and breakdown field. Further, the flat band voltage shift induced by positive voltage stress is reduced while keeping a low interface state density. Such advantages are correlated to trench MOSFET performance improvement.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 4","pages":"750-757"},"PeriodicalIF":2.5,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148464558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0