IEEE Transactions on Semiconductor Manufacturing最新文献_第8页

Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits 为现代集成电路开创快速安全的低 k 值二氧化硅合成技术

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-07 DOI: 10.1109/TSM.2024.3374067

Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu

{"title":"Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits","authors":"Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu","doi":"10.1109/TSM.2024.3374067","DOIUrl":"10.1109/TSM.2024.3374067","url":null,"abstract":"With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"185-189"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140073978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique 等离子体增强原子层沉积 SiN 在应力记忆技术中显著改善负偏压热不稳定性的使用寿命

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-07 DOI: 10.1109/TSM.2024.3397814

Cheng-Hao Liang;Zhao-Yang Li;Hao Liu;Yu-Long Jiang

引用次数: 0

Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation 循环中的专家：基于深度学习的条件变量选择，加速硅后验证

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-06 DOI: 10.1109/TSM.2024.3373690

Yiwen Liao;Raphaël Latty;Bin Yang

{"title":"Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation","authors":"Yiwen Liao;Raphaël Latty;Bin Yang","doi":"10.1109/TSM.2024.3373690","DOIUrl":"10.1109/TSM.2024.3373690","url":null,"abstract":"Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"199-206"},"PeriodicalIF":2.7,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140057229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Part-Level Fault Classification of Mass Flow Controller Drift in Plasma Deposition Equipment 等离子体沉积设备中质量流量控制器漂移的部件级故障分类

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-06 DOI: 10.1109/TSM.2024.3396994

Min Ho Kim;Hye Eun Sim;Sang Jeen Hong

{"title":"Part-Level Fault Classification of Mass Flow Controller Drift in Plasma Deposition Equipment","authors":"Min Ho Kim;Hye Eun Sim;Sang Jeen Hong","doi":"10.1109/TSM.2024.3396994","DOIUrl":"10.1109/TSM.2024.3396994","url":null,"abstract":"Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"373-380"},"PeriodicalIF":2.3,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140882583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask 利用锥形氧化硅掩模制造尖端顶点小于 5 纳米的高有序硅纳米锥阵列

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-04 DOI: 10.1109/TSM.2024.3372521

Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui

{"title":"Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask","authors":"Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui","doi":"10.1109/TSM.2024.3372521","DOIUrl":"10.1109/TSM.2024.3372521","url":null,"abstract":"In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"160-165"},"PeriodicalIF":2.7,"publicationDate":"2024-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140037422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Semantic Segmentation for Noisy and Limited Wafer Transmission Electron Microscope Images 噪声和有限晶片透射电子显微镜图像的语义分割

IF 2.3 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-03 DOI: 10.1109/TSM.2024.3396423

Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim

{"title":"Semantic Segmentation for Noisy and Limited Wafer Transmission Electron Microscope Images","authors":"Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim","doi":"10.1109/TSM.2024.3396423","DOIUrl":"10.1109/TSM.2024.3396423","url":null,"abstract":"Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"345-354"},"PeriodicalIF":2.3,"publicationDate":"2024-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140831626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Lightweight Chip-Scale Chemical Mechanical Polishing Model Based on Polynomial Network 基于多项式网络的轻量级芯片级化学机械抛光模型

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-26 DOI: 10.1109/TSM.2024.3370175

Ruian Ji;Rong Chen;Lan Chen

引用次数: 0

Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber 二氧化硅沉积室的环保干洗和诊断技术

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-14 DOI: 10.1109/TSM.2024.3365827

Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong

{"title":"Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber","authors":"Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong","doi":"10.1109/TSM.2024.3365827","DOIUrl":"10.1109/TSM.2024.3365827","url":null,"abstract":"Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"207-221"},"PeriodicalIF":2.7,"publicationDate":"2024-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Curvilinear Standard Cell Design for Semiconductor Manufacturing 用于半导体制造的曲线标准单元设计

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-06 DOI: 10.1109/TSM.2024.3362900

Ryoung-Han Kim;Soobin Hwang;Apoorva Oak;Yasser Shirazi;Hsinlan Chang;Kiho Yang;Gioele Mirabelli

{"title":"Curvilinear Standard Cell Design for Semiconductor Manufacturing","authors":"Ryoung-Han Kim;Soobin Hwang;Apoorva Oak;Yasser Shirazi;Hsinlan Chang;Kiho Yang;Gioele Mirabelli","doi":"10.1109/TSM.2024.3362900","DOIUrl":"10.1109/TSM.2024.3362900","url":null,"abstract":"Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"152-159"},"PeriodicalIF":2.7,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139945816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

IEEE Transactions on Semiconductor Manufacturing Information for Authors IEEE Transactions on Semiconductor Manufacturing 为作者提供的信息

IF 2.7 3区工程技术

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-02-05 DOI: 10.1109/TSM.2023.3334414

引用次数: 0