IEEE Transactions on Semiconductor Manufacturing最新文献

{"title":"Defect Reduction and Line Width Roughness Improvement by Using a Post Precoat Treatment in Waferless Chamber Conditioning","authors":"Jeff J. Ye;Raviteja Pagadala;Fei Lu","doi":"10.1109/TSM.2025.3535145","DOIUrl":"https://doi.org/10.1109/TSM.2025.3535145","url":null,"abstract":"Defect and line width roughness (LWR) are two main yield detractors in advanced plasma etch process in high-volume memory manufacturing. In this paper, we present the results of defect reduction and LWR improvement by using a post pre-coat treatment (PPT) method in waferless chamber clean (WCC) recipe. Adding a PPT step at the end of WCC recipe reduces defect, inline critical dimension (CD) variation and LWR. Atomic force microscopy (AFM) results show pre-coat silicon oxide and/or PPT improves surface roughness by 30%. X-ray photoelectron spectroscopy (XPS) has been utilized to characterize the surfaces treated with and without PPT, indicating PPT can remove residue chloride and solidify SiO2 film from its loose form. With the implementation of WCC with PPT, we have achieved yield improvement, which is attributed to defect reduction, tighter inline CD and LWR improvement.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"399-403"},"PeriodicalIF":2.3,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process Control in Semiconductor Manufacturing Based on Deep Distributional Soft Actor-Critic Reinforcement Learning","authors":"Bangxu Liu;Dewen Zhao;Xinchun Lu;Yuhong Liu","doi":"10.1109/TSM.2025.3539223","DOIUrl":"https://doi.org/10.1109/TSM.2025.3539223","url":null,"abstract":"The quality of semiconductor fabrication processes is typically degraded by variations in the manufacturing environment, which can be suppressed by run-to-run (R2R) control schemes. The performance of controlling systems to the produce process which is always highly complex and nonlinear physical model thus is strongly associated with the controlling strategy. However, previous works focusing on less complex semiconductor fabrication processes or linear controlling strategy are both hard to extend the application scenario. A novel structure for a R2R control system based on a distributed form of deep reinforcement learning (DRL), namely, distributional soft actor-critic (DSAC) DRL with twin-value distribution learning, is proposed for multizone pressure control in the chemical mechanical planarization (CMP) process, which is one of the most crucial manufacturing processes for the fabrication of ultra-large integrated circuits (ICs). In addition, several optimization algorithms for DRL, such as twin value distribution learning, are applied, further improving DSAC DRL to enhance the control performance. Compared with other reinforcement learning (RL)-based controllers, the proposed RL control policy achieves better control performance when tested using a multizone CMP virtual metrology (VM) model based on long short-term memory (LSTM) and one-dimensional convolutional neural network (1DCNN) architectures. This deep neural network (DNN) VM model, which is applied for the first time here to test the proposed DRL-based R2R controller for semiconductor manufacturing, is designed to preserve the complexity and nonlinearity of the CMP process by using data recorded from a practical manufacturing process at an IC fabrication facility in Tianjin, China. The novel model-free controlling schemes combined with the new VM model can be used in different R2R application scenarios. Meanwhile the results achieved using the proposed DRL control strategy strongly support its potential application in modern industrial semiconductor manufacturing and offer practical guidance for the further development of CMP procedures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"210-231"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress-Related Local Layout Effects in FinFET Technology and Device Design Sensitivity","authors":"Angelo Rossoni;Tomasz Brozek;Sharad Saxena;Rajesh Khamankar;Luigi Colalongo;Zsolt M. Kovacs-Vajna","doi":"10.1109/TSM.2025.3540267","DOIUrl":"https://doi.org/10.1109/TSM.2025.3540267","url":null,"abstract":"Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modulated by device design and local/ global environment. In this paper we investigate the impact of stress, developed during FinFET device fabrication, on electrical characteristics of transistors manufactured in 7nm silicon FinFET technology. Two sources of stress modulation are studied: (i) active region isolation (Diffusion Break) (ii) Metal Gate extension outside of the fins of the transistor. A 3D TCAD process model of a FinFET device was created and calibrated using electrical characteristics measured on foundry fabricated silicon wafers. The model was then applied to simulate mechanical stress in transistors with various design attributes for Diffusion Breaks (Single vs. Double Diffusion Break) and Gate Cuts, following by modeling of electrical characteristics. Very good agreement between simulations and measured silicon data has been obtained for PMOS and NMOS FinFET transistors. This work demonstrates that the layout sensitivity in discussed design cases can be explained by modulation of the mechanical stress and that the model can be used to predict successfully the stress distributions and their impact on electrical characteristics of FinFET devices. It can be applied to assist designers and technologists with Design-Technology Co-optimization, design rule and PDK development, and process optimization for best performance and reduced variability.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"117-125"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced Silicon Crystallization on Dielectric Materials at Reduced Temperature","authors":"Kangjian Cheng;Jingyan Huang;Wen Siang Lew","doi":"10.1109/TSM.2025.3539456","DOIUrl":"https://doi.org/10.1109/TSM.2025.3539456","url":null,"abstract":"We report the demonstration of the crystallization of amorphous arsenic and boron-doped silicon films on dielectric substrates at reduced thermal budgets. The conventional methods to form polycrystalline silicon generally require growth temperatures of at least <inline-formula> <tex-math>$600~^{circ }$ </tex-math></inline-formula>C, or high-temperature post-annealing to transform the silicon structure from amorphous into polycrystalline. Here, we show the formation of high-quality polycrystalline silicon at temperatures between <inline-formula> <tex-math>$500~^{circ }$ </tex-math></inline-formula>C and <inline-formula> <tex-math>$550~^{circ }$ </tex-math></inline-formula>C, which helps to reduce the thermal budget strain on heterojunction bipolar transistor devices. This advancement is attained by selecting buffer layer materials and fine-tuning film thickness. A notable increase in the film conductivity was observed, with improvements of 66% and 1719% for arsenic and boron-doped silicon films, respectively, compared to structured-mixed silicon films. The crystalline nature of the films is confirmed through top-view scanning electron microscopy coupled with ImageJ software analysis, offering a rapid, inline approach for crystal percentage quantification. Additionally, cross-sectional transmission electron microscopy analyses verify the complete film crystallization.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"203-209"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast and Accurate EUVL Thick-Mask Model Based on Multi-Channel Attention Network","authors":"Chengzhen Yu;Sheng Liu;Wensheng Chen;Xu Ma","doi":"10.1109/TSM.2025.3539300","DOIUrl":"https://doi.org/10.1109/TSM.2025.3539300","url":null,"abstract":"Simulation of thick-mask effects is an important task in computational lithography within extreme ultraviolet (EUV) waveband. This paper proposes a fast and accurate learning-based thick-mask model dubbed multi-channel block attention network (MCBA-Net) to solve this problem for EUV lithography. The proposed MCBA-Net introduces geometric feature attention module and structural feature attention module to improve the computation accuracy of thick-mask diffraction near field. During the training process, the proposed attention modules can effectively learn the impact of the three-dimensional mask diffraction behavior. In addition, the multi-channel network architecture is used to simultaneously synthesize the thick-mask diffraction matrices under different polarization states, and the coupling between different diffraction matrices is addressed. Numerical experiments show that the proposed model improves the computational efficiency by more than 20-fold over the rigorous simulator, and reduces the prediction error by 25%~50% compared with the state-of-the-art deep learning models. In addition, the generalization ability of the proposed method is proved using a complex testing pattern.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"194-202"},"PeriodicalIF":2.3,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Virtual Metrology of Multiple Dielectric Layer Thickness for 3D-NAND Deposition Process","authors":"Hye Eun Sim;Min Uk Lee;Sang Jeen Hong","doi":"10.1109/TSM.2025.3537974","DOIUrl":"https://doi.org/10.1109/TSM.2025.3537974","url":null,"abstract":"With the growing emphasis on three-dimensional (3D) vertical structures for enhancing the storage capacity and performance of 3D-NAND flash memory devices, precise control and prediction of process results to minimize process variability are important. Herein we predicted the layer thickness of an oxide/nitride (ON) dielectric stack for a 3D-NAND deposition process using artificial intelligence (AI). We investigated the key variables influencing the thicknesses of multiple dielectrics to propose strategies for mitigating thickness variation. We constructed a virtual metrology (VM) model based on status-variable identification (SVID) and optical emission spectroscopy (OES) data collected from plasma deposition equipment, and employed explainable AI (XAI) algorithms to interpret the significance of variables affecting the process results. XAI also supports the reliability of AI-predictive models for determining the thicknesses of the deposited multi-layered ON stack. Using variables derived from the SVID and OES data, the models for predicting oxide layer thickness, nitride layer thickness, and the thicknesses of both oxide and nitride layers achieved accuracies of 99%, 88% and 99%, respectively. This study highlights the importance of developing high-performance VM models and interpreting predictive outcomes for precise process control in semiconductor plasma processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"240-250"},"PeriodicalIF":2.3,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transfer Learning-Based Defect Detection System on Wafer Surfaces","authors":"Shou-Lin Chu;Eugene Su;Chao-Ching Ho","doi":"10.1109/TSM.2025.3532897","DOIUrl":"https://doi.org/10.1109/TSM.2025.3532897","url":null,"abstract":"This study addresses the significant decline in the accuracy of wafer inspection models when the imaging system changes post-training. We propose a domain adaptation method based on semantic segmentation models that maintains accuracy without the need for re-labeling data despite changes in the imaging system. This method was tested on wafers from an actual production line under two different detection environments: a custom-built simple optical system (source domain) and a precision measurement platform (target domain). To align the source and target domain datasets, we introduced an image preprocessing method that adjusts the contrast and brightness of the source domain data based on the histogram distribution of the target domain. We utilized adversarial learning to transfer features from the source to the target domain and modified the segmentation network architecture to prevent overfitting to the source domain data. Additionally, we extended the domain adaptation framework to handle multiple target domains using a multi-discriminator network strategy, enhancing the model’s adaptability to diverse production line environments. Our results demonstrate that compared to the original network, our model significantly improves accuracy with increases of 4.3%, 16.3%, and 11.4% for three different depths of the semantic segmentation model. Furthermore, our proposed network outperforms widely used style transfer methods with performance improvements of 13.2% and 17.3%. Post-processing the output segmentation maps yielded accuracy, precision, and recall scores of 96.8%, 93.5%, and 100%, respectively.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"154-167"},"PeriodicalIF":2.3,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deep Clustering and Regression Ensemble Network for Lot Cycle Time Prediction in Semiconductor Wafer Fabrication","authors":"Beomseok Song;Seunghwan Song;Jun-Geol Baek","doi":"10.1109/TSM.2025.3532300","DOIUrl":"https://doi.org/10.1109/TSM.2025.3532300","url":null,"abstract":"Accurate cycle time (CT) prediction is crucial in semiconductor manufacturing. Hybrid models integrating classification and prediction models can enhance CT prediction accuracy. However, existing methods have limitations, including challenges in capturing the dynamic conditions of the production line and optimizing job classification to ensure high CT prediction performance. In this study, we propose a novel hybrid framework for predicting process step-level CT in semiconductor wafer fabrication, thereby addressing the limitations of previous methods. Moreover, the paper formalizes and introduces dynamically changing manufacturing environment attributes as variables that contribute to CT. The proposed method combines deep embedded clustering (DEC) with a regression ensemble network. First, the DEC extracts cluster-friendly representative features from high-dimensional CT datasets and classifies jobs accordingly. Then, a weighted ensemble approach merges regression networks based on cluster membership probabilities. Unlike existing methods that separately handle feature extraction, job classification, and CT prediction, the proposed unified network synchronizes these processes. Experimental results using real-world operational data from a semiconductor manufacturing system indicate that the proposed prediction method considerably outperforms previous approaches in terms of prediction accuracy. To the best of our knowledge, this is the first study to integrate deep clustering with a regression ensemble network for predicting cycle time at the process step level in semiconductor manufacturing. By synchronizing feature extraction, clustering, and prediction tasks, the proposed framework achieves enhanced accuracy and robustness in dynamically changing manufacturing environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"281-291"},"PeriodicalIF":2.3,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stability Improvement of Power MOSFET-Driven Plasma Generation Device for Thin Film Deposition and Chamber Cleaning","authors":"Xiaogang Pan;Kangli Liu;Jianfeng Zhao;Cheng Jin;Guojun Zhu;Peiwen Zhu","doi":"10.1109/TSM.2025.3532355","DOIUrl":"https://doi.org/10.1109/TSM.2025.3532355","url":null,"abstract":"Regular removal of thin film depositions from vapor deposition chambers is a critical step in semiconductor manufacturing processes, directly impacting the efficiency and quality of production. Traditional manual disassembly cleaning methods have several drawbacks, including the necessity for shutdown operations, cooling treatment and breaking the vacuum, all of which consume considerable time and disrupt the production process. In contrast, plasma cleaning causes less damage to the chamber interior and has therefore become the preferred cleaning method. However, maintaining plasma stability requires a drive power supply with consistent current and frequency to prevent plasma extinction. In this article, the electrical characteristics of the drive power supply for the plasma generation device (PGD) are discussed, considering its dynamic and nonlinear load characteristics of plasma. Through analysis of the equivalent circuit, the condition of current gain equal to 1 is analyzed, thereby achieving the constant-current output. A Power MOSFET-based test platform was established and experimental results validate the effectiveness of the analysis.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"352-355"},"PeriodicalIF":2.3,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comparative Study of Semiconductor Virtual Metrology Methods and Novel Algorithmic Framework for Dynamic Sampling","authors":"Xu Han;Marcella Miller;James Moyne;Gregory William Vogl;Anita Penkova;Xiaodong Jia","doi":"10.1109/TSM.2025.3531920","DOIUrl":"https://doi.org/10.1109/TSM.2025.3531920","url":null,"abstract":"Virtual metrology (VM) is an important technology in semiconductor manufacturing that enhances process control, reduces costs, and improves quality. However, as processes become more complicated and process variations increase due to high-mix manufacturing, VM still faces challenges such as sensor drift and shift, as well as limited availability of metrology data due to high costs. This paper proposes an online Gaussian process (OGP) model designed to operate effectively with minimal initial metrology data and adapt dynamically to new data. The OGP model incorporates uncertainty quantification to optimize the sampling process, thereby enabling an adaptive sampling strategy to conduct metrology based on the process control needs. The proposed method is validated using a public dataset from the chemical mechanical planarization (CMP) process, demonstrating its effectiveness in tracking data drift and shift while reducing the required metrology data to retain model performance in an online operation setting.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"232-239"},"PeriodicalIF":2.3,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}