IEEE Transactions on Device and Materials Reliability最新文献_第5页

In-Field Testing of Functionally-Possible Transition Faults With High Activation Frequencies

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-26 DOI: 10.1109/TDMR.2024.3468710

Irith Pomeranz;Yervant Zorian

{"title":"In-Field Testing of Functionally-Possible Transition Faults With High Activation Frequencies","authors":"Irith Pomeranz;Yervant Zorian","doi":"10.1109/TDMR.2024.3468710","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468710","url":null,"abstract":"Motivated by the reliability requirements of chips in state-of-the-art technologies, this article develops an approach to periodic in-field testing that has the following features. The faults targeted are functionally-possible transition faults, implying that the faults can affect the correct functional operation of a chip. The fault sites in areas of the chip with higher switching activities during functional operation are considered important to target more often. This is because a higher switching activity can lead to faster aging, and therefore, a higher likelihood for defects. Under the approach described in this article, the computation of the functional switching activity, the identification of functionally-possible transition faults, and the generation of tests that are applicable in-field, are performed using the same set of functional test sequences. Experimental results for benchmark circuits demonstrate that small numbers of tests are sufficient for detecting functionally-possible transition faults in areas with high switching activities, making it possible to apply the tests frequently during the lifetime of the chip.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"4-10"},"PeriodicalIF":2.5,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A SiC Trench Schottky Diode With Accelerated Hole Extraction and Recombination Structure for Enhancing Single-Event Burnout Tolerance 一种具有加速孔提取和复合结构的碳化硅沟槽肖特基二极管，用于提高单事件灼烧容忍度

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-26 DOI: 10.1109/TDMR.2024.3468468

Rui Yang;Xiaochuan Deng;Haibo Wu;Xu Li;Xuan Li;Song Bai;Yi Wen;Bo Zhang

{"title":"A SiC Trench Schottky Diode With Accelerated Hole Extraction and Recombination Structure for Enhancing Single-Event Burnout Tolerance","authors":"Rui Yang;Xiaochuan Deng;Haibo Wu;Xu Li;Xuan Li;Song Bai;Yi Wen;Bo Zhang","doi":"10.1109/TDMR.2024.3468468","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468468","url":null,"abstract":"A SiC trench junction barrier Schottky diode with multiple P-shield layers and an embedded N+ region (MPNT-JBS) is proposed and investigated for enhancing single-event burnout (SEB) tolerance. The Schottky contact at the sidewall of the trench and the embedded N+ region in MPNT-JBS accelerate the extraction and recombination of holes. The mitigated accumulation of holes contributes to the reduction of the strong electric field near the metal/SiC interface, thus favoring a decrease in the high temperature. Under 50% of the rated voltage (\u0000<inline-formula> <tex-math>$V_{mathrm { Cathode}}{=}600$ </tex-math></inline-formula>\u0000 V), the maximum temperature near the metal/SiC interface in MPNT-JBS decreases by 78% and 71% compared to SiC JBS diode with multilayer N-buffer (MB-JBS), corresponding to the instances when heavy ions with a linear energy transfer (LET) value of 0.53 pC/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m strike the middle of the Schottky contact and the P+ region, respectively. In addition, the multilayer P-shield of MPNT-JBS suppresses the peak temperature near the PN junction by enlarging the energy dissipation area and lowering the transient heat power near the PN junction. Compared to MB-JBS, the maximum temperature near the PN junction in MPNT-JBS decreases from 1890 K to 1454 K when heavy ions strike the middle of the P+ region (\u0000<inline-formula> <tex-math>$V_{mathrm { Cathode}}{=}600$ </tex-math></inline-formula>\u0000 V). These results indicate that MPNT-JBS provides potential for enhancing SEB tolerance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"549-555"},"PeriodicalIF":2.5,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication 重复热应力法在CMOS工艺中氘钝化的研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-25 DOI: 10.1109/TDMR.2024.3467249

Ju-Won Yeon;Sung-Su Yoon;Hyo-Jun Park;Tae-Hyun Kil;Dong-Hyun Wang;Khwang-Sun Lee;Dae-Han Jung;Ja-Yun Ku;Jun-Young Park

{"title":"Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication","authors":"Ju-Won Yeon;Sung-Su Yoon;Hyo-Jun Park;Tae-Hyun Kil;Dong-Hyun Wang;Khwang-Sun Lee;Dae-Han Jung;Ja-Yun Ku;Jun-Young Park","doi":"10.1109/TDMR.2024.3467249","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467249","url":null,"abstract":"High-pressure deuterium annealing (HPDA) has been proposed as a promising process to enhance device performance and reliability. However, additional thermal stress after the HPDA can lead to de-passivation of Si-D bonds at the gate dielectric interface. In this study, electrical characterization of deuterium annealed MOSFETs after repetitive thermal stress conditions is performed to obtain guidelines for conducting post-metal annealing. MOSFETs are fabricated on silicon wafer to verify the passivation as well as de-passivation of deuterium. Device parameters including subthreshold swing (SS), on-state current \u0000<inline-formula> <tex-math>$(I_{mathrm { ON}})$ </tex-math></inline-formula>\u0000, off-state current \u0000<inline-formula> <tex-math>$(I_{mathrm { OFF}})$ </tex-math></inline-formula>\u0000, and gate leakage \u0000<inline-formula> <tex-math>$(I_{mathrm { G}})$ </tex-math></inline-formula>\u0000, are comprehensively compared. Finally, hot-carrier injection (HCI) stress is applied to compare the changes in stress immunity resulting from deuterium de-passivation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"618-623"},"PeriodicalIF":2.5,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Failure Mechanism of Internal Circuit During ESD Striking a Power to Another Power ESD对电源冲击时内部电路的失效机理

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-24 DOI: 10.1109/TDMR.2024.3467116

Chih-Cherng Liao;Ching-Ho Li;Karuna Nidhi;Chieh-Yao Chuang;Hsien-Feng Liao;Yeh-Ning Jou;Ke-Horng Chen;Jian-Hsing Lee

引用次数: 0

Comparative Analysis of SGTMOS Degradation Under Repeated Off-State Avalanche and Short Circuit Current Pulses 重复断态雪崩和短路电流脉冲下SGTMOS退化的比较分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-24 DOI: 10.1109/TDMR.2024.3467096

Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang

{"title":"Comparative Analysis of SGTMOS Degradation Under Repeated Off-State Avalanche and Short Circuit Current Pulses","authors":"Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang","doi":"10.1109/TDMR.2024.3467096","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467096","url":null,"abstract":"In this article, a 60-V split-gate trench vertical double diffused metal-oxide-semiconductor field-effect transistor (SGTVDMOS, SGTMOS) with low on-resistance is designed and manufactured. The device adopts an ultra-deep split gate trench with a grounded bottom shield gate. The electrical parameters degradations subsequent to repeated off-state avalanche and short circuit current pulses are investigated and compared for the first time. After avalanche voltage stress, crucial parameters such as threshold voltage (Vt), Miller capacitance (CGD) remain unaffected. However, a noteworthy change is observed in blocking characteristics, manifested as an increase in breakdown voltage. Conversely, after subjecting the device to short-circuit pulse current stress, a minor reduction in \u0000<inline-formula> <tex-math>$rm V_{t}$ </tex-math></inline-formula>\u0000 is noted, while the breakdown characteristics remain constant. Technology computer-aided design (TCAD) simulation and actual test analysis are combined to reveal the degradation mechanism, it has been determined that electron injection degradation occurs under both stresses. However, distinct degradation phenomena occur due to the disparate positions of electron injection. During avalanche stress, electrons within the polysilicon (shield gate) tunnel into the oxide layer of the bottom shielding gate, while hot electron injection occurs near the active trench gate during a continuous short-circuit pulses.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"596-601"},"PeriodicalIF":2.5,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High Sensitivity Temperature Measurements to Track and Compensate Aging Effects on CMOS Amplifiers 通过高灵敏度温度测量跟踪和补偿 CMOS 放大器的老化效应

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-23 DOI: 10.1109/TDMR.2024.3465236

Diego Mateo;Xavier Aragones;Enrique Barajas;Sergio Martínez Domingo;Xavier Gisbert;Josep Altet

引用次数: 0

Improving Single-Event Effect Performance of SiC MOSFET by Excess Hole Extraction 利用多余空穴提取提高SiC MOSFET单事件效应性能

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-19 DOI: 10.1109/TDMR.2024.3463698

Shiwei Liang;Yu Yang;Jiaqi Chen;Lei Shu;Liang Wang;Jun Wang

{"title":"Improving Single-Event Effect Performance of SiC MOSFET by Excess Hole Extraction","authors":"Shiwei Liang;Yu Yang;Jiaqi Chen;Lei Shu;Liang Wang;Jun Wang","doi":"10.1109/TDMR.2024.3463698","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3463698","url":null,"abstract":"Heavy ion strike-induced Single-Event Effect (SEE) is an essential reliability issue for SiC MOSFETs in radiation environments. The mass clustering of excess charges in SiC MOSFET is found to be root cause for device failure when heavy ion strikes. Based on the SEE failure mechanism, a planar gate SiC MOSFET with Hole Extraction Channel (HEC-MOS) and current aperture structure to improve its SEE immunity and electrical performance is proposed in this paper. The embedded \u0000<inline-formula> <tex-math>$P^{+}$ </tex-math></inline-formula>\u0000 pillar provides an additional path to extract excess holes during heavy ion radiation so that transient currents and SEE response time are greatly reduced. As a result, the maximum lattice temperature (hot spot) decreases by 768K, and a single-event burnout (SEB) threshold voltage of 624V is achieved with linear energy transfer (LET) value of 75MeV\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000cm2/mg for HEC-MOS, which is 1.4 times higher than conventional SiC MOSFET (Conv-MOS). Moreover, the gate oxide electric field also decreases ~10 times owing to much less clustered holes in JFET region, which ensures HEC-MOS superior immunity to single-event gate rupture (SEGR). Apart from improving SEE performance, a better trade-off with its electrical performances is also considered. By adopting optimized parameters in current spreading layers and P+ pillar, the specific ON-resistance of HEC-MOS is reduced by 17.5% while maintain a good forward blocking capability and SEB immunity. Therefore, HEC-MOS is a promising candidate for harsh environmental applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"507-513"},"PeriodicalIF":2.5,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability Analysis of GaAs-PIN Limiter Under Ultra-Wideband Pulse Radiation 超宽带脉冲辐射下 GaAs-PIN 限幅器的可靠性分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-10 DOI: 10.1109/TDMR.2024.3456832

Xuelin Yuan;Shengxian Chen;Yonglong Li;Ming Hu;Teng Zhou

{"title":"Reliability Analysis of GaAs-PIN Limiter Under Ultra-Wideband Pulse Radiation","authors":"Xuelin Yuan;Shengxian Chen;Yonglong Li;Ming Hu;Teng Zhou","doi":"10.1109/TDMR.2024.3456832","DOIUrl":"10.1109/TDMR.2024.3456832","url":null,"abstract":"With the increasing complexity of electromagnetic environments, receivers demand higher reliability from their internal components. To enhance the survivability of receivers, limiter circuits are commonly inserted at the backend of antennas to mitigate the damage caused by high-power interference pulses to subsequent sensitive components. The reliability of limiter circuits determines the stable operation of sensitive components at the backend, which holds significant implications for the overall reliability and robustness of navigation receivers. Given that Ultra-Wideband (UWB) pulse’s temporal characteristics typically last on the order of sub-nanoseconds, they can substantially influence the performance of limiter circuits. This study employs UWB-EMP as the interfering pulse to investigate the failure process and mechanism of the core device, GaAs-PIN diode, within the PIN limiter under UWB pulse exposure. Simulation results indicate that the failure of the diode’s conductivity modulation effect under UWB pulse exposure leads to the incapacity of the PIN limiter to function properly. Furthermore, the generation of multiple oscillatory pulses post-pulse exposure exacerbates the performance degradation of the PIN limiter. Experimental validations conducted via injection corroborate the simulation outcomes, demonstrating the impact of failure mechanisms and varying degrees of failure on normal signals within the PIN limiter.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"487-497"},"PeriodicalIF":2.5,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bound-Constrained Expectation Maximization for Weibull Competing-Risks Device Reliability 魏布尔竞争风险设备可靠性的有界约束期望最大化

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-10 DOI: 10.1109/TDMR.2024.3457728

Uttara Chakraborty;Duane S. Boning;Carl V. Thompson

{"title":"Bound-Constrained Expectation Maximization for Weibull Competing-Risks Device Reliability","authors":"Uttara Chakraborty;Duane S. Boning;Carl V. Thompson","doi":"10.1109/TDMR.2024.3457728","DOIUrl":"10.1109/TDMR.2024.3457728","url":null,"abstract":"Estimating the reliability of electronic devices involves identification of failure mechanisms and prediction of lifetimes. For parameter estimation and failure mode identification in Weibull competing-risks models, a differential-evolution-based global optimization approach has recently been developed, with the superiority of that approach demonstrated over the best-known local methods for the problem. In an effort to design a method faster than differential evolution for this problem, the present paper develops a new type of expectation maximization (EM) algorithm that is capable of handling bound constraints while optimizing the parameters of the Weibull component distributions. The differential-evolution-based approach guarantees a feasible, but not necessarily high-quality, solution in every run, while the proposed method offers no such guarantee. Despite this lack of guarantee, the proposed method is seen to produce results of a quality highly competitive with differential evolution. Numerical results on ten test cases, based on three real test datasets and two synthetic datasets, show that in terms of solution quality, the proposed method is competitive with differential evolution, while offering an average savings of about 64% in the computation time. Comparative performance analyses with the standard EM algorithm and the best-known local method L-BFGS-B are also provided. The numerical results are statistically validated. A new approach to model improvement via selective failure analysis is demonstrated as an application of the proposed algorithm. The proposed algorithm has the potential to be used for general-purpose likelihood maximization involving latent variables in diverse domains.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"556-570"},"PeriodicalIF":2.5,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research of Single-Event Burnout in P-NiO/n-Ga2O3 Heterojunction Diode P-NiO/n-Ga2O3 异质结二极管中的单次烧毁研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-09 DOI: 10.1109/TDMR.2024.3456095

Cheng-Hao Yu;Hui Yang;Wen-Sheng Zhao;Da-Wei Wang;Hao-Min Guo;Yue Hu;Xiao-Dong Wu;Xin Tan

{"title":"Research of Single-Event Burnout in P-NiO/n-Ga2O3 Heterojunction Diode","authors":"Cheng-Hao Yu;Hui Yang;Wen-Sheng Zhao;Da-Wei Wang;Hao-Min Guo;Yue Hu;Xiao-Dong Wu;Xin Tan","doi":"10.1109/TDMR.2024.3456095","DOIUrl":"10.1109/TDMR.2024.3456095","url":null,"abstract":"This paper presents the 2-D numerical simulation results of the ion-induced single-event burnout (SEB) in the conventional gallium-oxide (Ga2O3) Schottky barrier diode (SBD), conventional Ga2O3 heterojunction diode (HJD), and Ga2O3 HJD with a p-NiO junction termination extension (JTE) and a small-angle beveled field plate (BFP). The employed simulation physics models and material parameters are validated by the reverse I-V characteristics in experiments. The simulation results of SEB failure mechanism and threshold voltage in the conventional Ga2O3 SBD are proved by the chlorine (Cl) ion irradiation tests. The most sensitive position and the ion range influence to induce an SEB are discussed. Then, the SEB failure mechanism and threshold voltage of conventional Ga2O3 HJD are comparatively investigated based on the Cl ion strike. Although, the conventional HJD presents much better SEB performance than conventional SBD in anode position, the anode edge of HJD is proved to be very sensitive to an ion. Therefore, the Ga2O3 HJD with JTE and BFP, which can significantly suppress the peak electric field strength at the anode edge, is investigated that has better SEB performance than the conventional SBD and HJD under different ion species.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"480-486"},"PeriodicalIF":2.5,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0