IEEE Transactions on Device and Materials Reliability最新文献_第5页

Research on the Mechanism of Electrical Erosion Accelerating Failure in High-Current Pulse Thyristor-Based Switches 大电流脉冲晶闸管开关电侵蚀加速失效机理研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-29 DOI: 10.1109/TDMR.2025.3565618

Shiyun Xiao;Yi Liu;Liuxia Li;Fuchang Lin;Yunxin Miao

{"title":"Research on the Mechanism of Electrical Erosion Accelerating Failure in High-Current Pulse Thyristor-Based Switches","authors":"Shiyun Xiao;Yi Liu;Liuxia Li;Fuchang Lin;Yunxin Miao","doi":"10.1109/TDMR.2025.3565618","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3565618","url":null,"abstract":"High-current pulse thyristor-based switches operate under high-current pulse conditions and are subjected to coupled electromagnetic-thermomechanical stresses, resulting in the progressive development of thermal fatigue-induced failure mechanisms. The study revealed that localized overheating triggers electrical erosion of the aluminum layer, which further accelerates the thermal fatigue failure of high-current switches. To investigate this phenomenon, a microscopic model of the silicon-aluminum interface incorporating surface roughness effects was developed to quantify the transient temperature rise and electrical erosion threshold under varying pulsed current conditions, with experimental validation demonstrating strong agreement. Furthermore, using a thermal network model, we established a correlation between the electrical erosion threshold and the average junction temperature for different high-current pulses and clamping stresses, thereby defining the operational range for electrical erosion in high-current pulse thyristor-based switches. This provides theoretical guidance for the reliable operation of these switches.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"263-273"},"PeriodicalIF":2.5,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Memristive Switching Behavior of MoO3 Decorated PSi Heterostructure and Impact of Temperature on Device Reliability MoO3修饰PSi异质结构的忆阻开关行为及温度对器件可靠性的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-24 DOI: 10.1109/TDMR.2025.3563885

B Sharmila;Kr. Sarkar Achintya;Priyanka Dwivedi

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A Low Cost Triple-Node-Upset Self-Recoverable Latch Design for Nanoscale CMOS 纳米级CMOS低成本三节点扰流自恢复锁存器设计

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-16 DOI: 10.1109/TDMR.2025.3561519

Na Bai;Pengshuai Zhang;Yaohua Xu;Yunhui Guo;Hang Li;Yi Wang;Xiaoqing Wen

{"title":"A Low Cost Triple-Node-Upset Self-Recoverable Latch Design for Nanoscale CMOS","authors":"Na Bai;Pengshuai Zhang;Yaohua Xu;Yunhui Guo;Hang Li;Yi Wang;Xiaoqing Wen","doi":"10.1109/TDMR.2025.3561519","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3561519","url":null,"abstract":"Due to the constant reduction of semiconductor feature sizes, the charge sharing effect is getting worse. The occurrence probability of triple-node upset (TNU), which has a significant impact on the circuit’s reliability, is rising in nanoscale digital circuits. This paper proposes a low overhead and TNU self-recovery latch (TNU-SR) based on the 28 nm CMOS technology to efficiently tolerate TNU and reduce the power dissipation and latency of the latch. The latch design proposed in this article adopts stacked transistors to reduce sensitive nodes and area overhead. The TNU-SR latch uses clock gating and high-speed transfer path technology, resulting in low power dissipation and low delay. For simulation results, compared with existing latches, it can be known that the TNU-SR latch performs well in terms of delay, power consumption, and area, so it is a good choice for radiation-hardened design for space applications. In addition, compared with the latest TNU self-recovery latch (HLTNURL), the TNU-SR latch proposed in this paper reduces the Power-Area-Delay Product (PADP) metric by 111.13%.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"296-307"},"PeriodicalIF":2.5,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Power Grid Electromigration Test Chip for Lifetime Characterization and Model Calibration 一种用于寿命表征和模型校准的电网电迁移测试芯片

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-14 DOI: 10.1109/TDMR.2025.3560489

Yong Hyeon Yi;Robert Bloom;Armen Kteyan;Alexander Volkov;Jun-Ho Choy;Stephane Moreau;Valeriy Sukharev;Chris H. Kim

引用次数: 0

Modeling Degradation Kinetics of FAPbI₃ Perovskite Solar Cells: Impact of Microstructural and Optoelectronic Defects FAPbI₃钙钛矿太阳能电池的降解动力学建模：微观结构和光电子缺陷的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-10 DOI: 10.1109/TDMR.2025.3559531

Anand Pandey;Ankush Bag

{"title":"Modeling Degradation Kinetics of FAPbI₃ Perovskite Solar Cells: Impact of Microstructural and Optoelectronic Defects","authors":"Anand Pandey;Ankush Bag","doi":"10.1109/TDMR.2025.3559531","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3559531","url":null,"abstract":"The operational thermal stability of perovskite solar cells (PSCs) is a critical issue hindering their commercialization. Therefore, besides achieving high power conversion efficiency (PCE), understanding and quantifying the device degradation kinetics of PSCs is necessary for their reliability and to prevent failure under thermal stress. In this work, exponential and linear degradation models have been adopted to comprehend and quantify the degradation kinetics of FAPbI3 and multifunctional fluorinated molecule 3-fluoro-4-methoxy-4’,4”-bis((4-vinyl benzyl ether) methyl)) triphenylamine (FTPA)-modified FAPbI3 PSCs. Further, various figures of merit, such as acceleration factor, degradation factor, mean lifetime, transformational fraction, and activation energy, have been deduced by fitting the PCE degradation data into the Arrhenius equation and onto the Johnson– Mehl-Avrami (JMA) kinetic models. These figures of merit have been correlated with other defect-determining factors such as micro-strain and Urbach’s energy. The degradation factor and PbI2 residuals are reduced for controlled PSCs to FTPA-modified PSCs. Furthermore, the activation energy and operational thermal stability of FTPA-modified PSCs have increased due to the forming of a hydrogen-bonding polymer network, which enhances PSCs’ thermal stability and acceleration factor. Our findings reveal that the studied devices’ intrinsic stability, thermal stability, and mean lifetime strongly correlate with micro-structural and optoelectronic defects, which helps to improve the performance of photovoltaics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"288-295"},"PeriodicalIF":2.5,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Achievement of Pulse Laser Deposited Amorphous P-Type N-Doped Ga₂O₃ for Applying in Thin Film Transistor and Homojunction Diode 脉冲激光沉积非晶p型n掺杂Ga₂O₃在薄膜晶体管和同结二极管中的应用

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-09 DOI: 10.1109/TDMR.2025.3559225

Teng-Min Fan;Chen Wang;Cong Yi;Chen-Hao Zhou;Yu-Li Su;Yun-Shao Cho;Dong-Sing Wuu;Shui-Yang Lien

{"title":"The Achievement of Pulse Laser Deposited Amorphous P-Type N-Doped Ga₂O₃ for Applying in Thin Film Transistor and Homojunction Diode","authors":"Teng-Min Fan;Chen Wang;Cong Yi;Chen-Hao Zhou;Yu-Li Su;Yun-Shao Cho;Dong-Sing Wuu;Shui-Yang Lien","doi":"10.1109/TDMR.2025.3559225","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3559225","url":null,"abstract":"In this study, an amorphous p-type N-doped Ga2O3 thin film has been achieved using pulsed laser deposition and Ga2O3:GaN=1:1 (at%) mixed ceramic target. The bonding states of the films after nitrogen incorporation were investigated using X-ray photoelectron spectroscopy, which revealed the lattice oxygen sites substituted by nitrogen. Ultraviolet photoelectron spectroscopy analysis shows a p-type feature of N-doped Ga2O3 film and a weak n-type unintentional doped pure Ga2O3 film. The thin film transistors have been fabricated using pure and N-doped Ga2O3 films to further confirm their n-type and p-type conductive properties, respectively. The N-doped Ga2O3-based TFTs displays p-type characteristics with a field effect mobility of <inline-formula> <tex-math>$2.13times 10{^{text {-3}}}$ </tex-math></inline-formula> cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, an on/off ratio of <inline-formula> <tex-math>$2.78times 10{^{{4}}}$ </tex-math></inline-formula> and a sub-threshold swing of 0.15 V/dec. Finally, a full amorphous Ga2O3 films-based pn homojunction diode has been fulfilled and explored in detail, which displays a good rectifying characteristic with a rectification ratio of <inline-formula> <tex-math>$1.46times 10{^{{2}}}$ </tex-math></inline-formula> and an ideality factor of 5.19.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"281-287"},"PeriodicalIF":2.5,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Magnetically Coupled Resonant Wireless Power Transmission System: A Review of Fault Diagnosis Methods 磁耦合谐振无线输电系统：故障诊断方法综述

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-07 DOI: 10.1109/TDMR.2025.3558283

Fengchuan Wang;Cheng Chen;Zhihao Ye;Qikai Fang;Gang Yang

引用次数: 0

Die-Attach Influence on Thermal/Electrical Parameters of GaN RF Device 贴片对GaN射频器件热/电参数的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-01 DOI: 10.1109/TDMR.2025.3556383

Giacomo Cappellini;Giuseppe D’Arrigo;Viviana Cerantonio;Marcello Cioni;Alessandro Chini;Sonia Zappala;Simone Strano;Leonardo Gervasi;Marcello Giuffrida;Cristina Miccoli;Cristina Tringali;Maria Eloisa Castagna;Ferdinando Iucolano

{"title":"Die-Attach Influence on Thermal/Electrical Parameters of GaN RF Device","authors":"Giacomo Cappellini;Giuseppe D’Arrigo;Viviana Cerantonio;Marcello Cioni;Alessandro Chini;Sonia Zappala;Simone Strano;Leonardo Gervasi;Marcello Giuffrida;Cristina Miccoli;Cristina Tringali;Maria Eloisa Castagna;Ferdinando Iucolano","doi":"10.1109/TDMR.2025.3556383","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3556383","url":null,"abstract":"This paper presents a comprehensive study on the relation between die-attach and thermal/electrical parameters of GaN RF devices. This correlation is investigated through Multiphysics simulations and experimental data. Particularly, thermal analysis is performed by means of Quantum Focus Instrument (QFI) Infrascope able to detect the surface temperature of the device. Then, 3-D finite element method thermal simulations are performed to support the observed heat distribution. A strong association between drain current drift and temperature escalation is demonstrated by comparing two devices with significantly different die-attaches. Particularly, we observe an increase in the drain current with increasing self-heating effects, conversely to what generally expected for thermal derating. However, this correlation is then explained thanks to the analysis of threshold voltage shift with temperature that supports the experimental evidence.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"308-313"},"PeriodicalIF":2.5,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Dual-Mode Dual Trench MOSFET With Self-Adjustable Field Plate for Low EMI Noise and High Dynamic Avalanche Robustness 一种具有自调场极板的新型双模双沟槽MOSFET，具有低电磁干扰噪声和高动态雪崩鲁棒性

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-01 DOI: 10.1109/TDMR.2025.3556015

Tongyang Wang;Zehong Li;Yishang Zhao;Ziming Xia;Yige Zheng;Jun Ye;Xuan Xiao

{"title":"A Novel Dual-Mode Dual Trench MOSFET With Self-Adjustable Field Plate for Low EMI Noise and High Dynamic Avalanche Robustness","authors":"Tongyang Wang;Zehong Li;Yishang Zhao;Ziming Xia;Yige Zheng;Jun Ye;Xuan Xiao","doi":"10.1109/TDMR.2025.3556015","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3556015","url":null,"abstract":"A novel dual-mode dual trench MOSFET (DDT-MOSFET) featuring shorted P-doping field plate (PFP) and N-doping field plate (NFP) is proposed. A parasitic depletion region capacitor and a parasitic MOSFET are introduced in the self-adjustable field plate (SFP). During turn-on, the DDT-MOSFET is in the split gate trench (SGT) mode with an electron inversion layer in the PFP, achieving low <inline-formula> <tex-math>$C_{mathrm { gd}}$ </tex-math></inline-formula>. During turn-off, the DDT-MOSFET is in the insulator pillar superjunction (I-SJ) mode with depleted PFP, achieving low electromagnetic interference (EMI) noise and high breakdown voltage (BV). Mode conversion is realized by the introduction of the SFP. By TCAD simulation, during turn-off, the proposed structure exhibits 33.9% improvement in BV, 42.8% reduction in maximum <inline-formula> <tex-math>$dI_{mathrm { D}}$ </tex-math></inline-formula>/dt and 44.1% reduction in overshoot voltage <inline-formula> <tex-math>$(V_{mathrm { O}})$ </tex-math></inline-formula> with same <inline-formula> <tex-math>$E_{mathrm { off}}$ </tex-math></inline-formula>, reducing EMI noise and improving dynamic avalanche robustness without deterioration of other electrical characteristics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"274-280"},"PeriodicalIF":2.5,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Statistical Model and Transistor Size Effect of Hot Carrier Injection for Stability Reinforced SRAM Physically Unclonable Function 稳定性增强SRAM物理不可克隆功能的热载流子注入统计模型和晶体管尺寸效应

IF 2.3 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-29 DOI: 10.1109/TDMR.2025.3574796

Shufan Xu;Kunyang Liu;Kiichi Niitsu;Hirofumi Shinohara

{"title":"Statistical Model and Transistor Size Effect of Hot Carrier Injection for Stability Reinforced SRAM Physically Unclonable Function","authors":"Shufan Xu;Kunyang Liu;Kiichi Niitsu;Hirofumi Shinohara","doi":"10.1109/TDMR.2025.3574796","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574796","url":null,"abstract":"Hot carrier injection (HCI) has been strategically leveraged to enhance the stability of SRAM physically unclonable functions (PUFs). Since the effects of HCI are not constant, exhibiting cell-to-cell variability, a comprehensive distribution model is essential to harness HCI effectively. This article presents a statistical distribution model of mismatch after HCI burn-in and examines the impact of transistor size of PUF on the distribution shape, yielding enhanced stability and shorter HCI burn-in time. The proposed mismatch model after HCI burn-in integrates the native distribution with a Poisson distribution for number of captured electrons and a Gamma distribution for the effect of captured electrons. Model calculations based on size effects reveal that over three times reduction in HCI burn-in duration by enhancing the size to quadruple times: a 15-min for quadruple-size transistor SRAM PUF compared to 46-min for single-size PUF. The model is confirmed by the real chip measurement. The PUFs with several sized transistors are fabricated in a 130-nm standard CMOS process. Experimental results show that quadruple-size transistor SRAM PUF reaches 1.82E−09 unstable cell ratio after 18-min HCI burn-in, which align with the model based expectation. Furthermore, robust stability is exhibited even the worst VT corner (0.6V / <inline-formula> <tex-math>$-40^{circ }mathrm {C}$ </tex-math></inline-formula>), demonstrating zero bit error (BER<7.81E−08).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"481-491"},"PeriodicalIF":2.3,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017744","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0