IEEE Transactions on Device and Materials Reliability最新文献_第5页

Suppression of Total Dose Effects on the Performance of InAlGaN/GaN MIS-HEMT via Field Plate Implementation 通过场板实现抑制总剂量对 InAlGaN/GaN MIS-HEMT 性能的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-07-05 DOI: 10.1109/TDMR.2024.3422326

Yi-En Chang-Chien;Chin-Han Chung;Chih-Yi Yang;Cheng-Jun Ma;Xiang-You Ye;You-Chen Weng;Edward Yi Chang

{"title":"Suppression of Total Dose Effects on the Performance of InAlGaN/GaN MIS-HEMT via Field Plate Implementation","authors":"Yi-En Chang-Chien;Chin-Han Chung;Chih-Yi Yang;Cheng-Jun Ma;Xiang-You Ye;You-Chen Weng;Edward Yi Chang","doi":"10.1109/TDMR.2024.3422326","DOIUrl":"10.1109/TDMR.2024.3422326","url":null,"abstract":"In this study, quaternary InAlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) aimed for power applications were exposed to 800 krad of Co\u0000<inline-formula> <tex-math>$^{60}~gamma $ </tex-math></inline-formula>\u0000-ray, and their response to total dose effects was recorded. For the irradiation process, devices with five gate-connected field plate schemes of field plate length (without field plate, \u0000<inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>\u0000 m, 4, \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m, \u0000<inline-formula> <tex-math>$6~mu $ </tex-math></inline-formula>\u0000 m, \u0000<inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>\u0000 m) were tested under either a grounded state or a stressed state. It was discovered that the implementation of the field plate could successfully suppress the virtual gate phenomenon exacerbated by total dose effects. Post-irradiation analysis of the reverse characteristics also revealed that for devices irradiated under a stressed state, field plates could increase the device robustness against total dose effects impacting the electrical breakdown.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"407-413"},"PeriodicalIF":2.5,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141575407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Single-Event Burnout Effects of Complementary LDMOS Devices in High-Voltage Integrated Circuits 高压集成电路中互补 LDMOS 器件的单次烧毁效应

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-28 DOI: 10.1109/TDMR.2024.3420391

Chonghao Chen;Jiang Xu;Zhuojun Chen

{"title":"Single-Event Burnout Effects of Complementary LDMOS Devices in High-Voltage Integrated Circuits","authors":"Chonghao Chen;Jiang Xu;Zhuojun Chen","doi":"10.1109/TDMR.2024.3420391","DOIUrl":"10.1109/TDMR.2024.3420391","url":null,"abstract":"Lateral diffused metal-oxide-semiconductor (LDMOS) devices are vulnerable to single-event burnout (SEB) in radiation environments, potentially leading to catastrophic failure in high-voltage integrated circuits (HVICs). Pulsed-laser experiments have demonstrated that the SEB triggering voltage of n-type LDMOS (nLDMOS) is significantly lower than that of p-type LDMOS (pLDMOS), which limits the applications of complementary LDMOS devices in aerospace electronic systems. This work investigates the SEB mechanism in both nLDMOS and pLDMOS through technology computer-aided design (TCAD) simulations. The analysis reveals that differences in the current gain of parasitic bipolar transistors and well resistance between pLDMOS and nLDMOS result in varying SEB triggering voltages. Additionally, a radiation-hardening technique is employed to improve the SEB triggering voltage of nLDMOS, aligning it closely with that of pLDMOS. This research provides insight into the design of radiation-hardened high-voltage integrated circuits, such as DC-DC converters and motor drivers, using a standard Bipolar-CMOS-DMOS (BCD) fabrication process.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"401-406"},"PeriodicalIF":2.5,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Prediction of Crack Initiation at Die Corner of Molded Underfill Flip-Chip Packages Under Thermal Load by New Criteria 通过新标准预测热负荷下模制底部填充倒装芯片封装模具边角处的裂纹萌生--第 I 部分：奇异应力场的精确表述

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-28 DOI: 10.1109/TDMR.2024.3420759

G. C. Lyu;X. P. Zhang;M. B. Zhou;C. B. Ke;Y. W. Mai

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Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique 结合布局硬化技术设计高可靠性 14T 和 16T SRAM 单元

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-24 DOI: 10.1109/TDMR.2024.3417961

Feng Wei;Xiaole Cui;Qixue Zhang;Sunrui Zhang;Xiaoxin Cui;Xing Zhang

{"title":"Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique","authors":"Feng Wei;Xiaole Cui;Qixue Zhang;Sunrui Zhang;Xiaoxin Cui;Xing Zhang","doi":"10.1109/TDMR.2024.3417961","DOIUrl":"10.1109/TDMR.2024.3417961","url":null,"abstract":"The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve its ability of recovering from the undesired node upset. However, the extra redundant transistors may increase the number of sensitive nodes in the SRAM cell, which decreases its capability of node-upset tolerance in turn. This work proposes an RHBD 14T SRAM cell and an RHBD 16T SRAM cell. Both the proposed SRAM cells only have two sensitive nodes. The proposed SRAM cells are able to recover from all the SNU cases. The layout harden technique is used to protect the proposed cells from SEMNU, and the blank of the hardened layout is reused so the proposed 14T and 16T SRAM cells consume the same area. Although the proposed cells have more transistors, the hardened layout areas of NS-10T/ PS-10T/ RHD-12T/ RHBD-10T/ RHBD-10T[VLSI]/ QUCCE-12T are respectively \u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.83times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.99times $ </tex-math></inline-formula>\u0000 larger than that of the proposed cells. The reason is that the layout harden technique is easier to be applied to the proposed cells because they only have two sensitive nodes.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"390-400"},"PeriodicalIF":2.5,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Special Issue on Intelligent Sensor Systems for the IEEE Journal of Electron Devices 电气和电子工程师学会电子器件期刊》智能传感器系统特刊

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405612

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Blank Page 空白页

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405820

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IEEE Transactions on Device and Materials Reliability Information for Authors IEEE 《器件与材料可靠性》期刊为作者提供的信息

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405819

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Guest Editorial TDMR IIRW Special Section 特约编辑 TDMR IIRW 特辑

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3407548

Charles LaRow

{"title":"Guest Editorial TDMR IIRW Special Section","authors":"Charles LaRow","doi":"10.1109/TDMR.2024.3407548","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3407548","url":null,"abstract":"The IEEE International Integrated Reliability Workshop (IIRW) is a distinctive event which brings together reliability researchers, professionals, and students from around the globe to a common forum for lively discussions, wonderful technical presentations, and beautiful scenery for 4 days and nights. The event takes place every year at Fallen Leaf Lake in South Lake Tahoe, CA, USA, where attendees are housed within a secluded camp with informal meeting spaces and access to boats, trails, and many other outdoor activities. The scope of content centers around hot topics in, novel techniques for, and general knowledge on semiconductor reliability research and industry challenges. Talks on transistor and front-end-of-the-line (FEOL) reliability, bias temperature instability (BTI), hot carrier (HC), gate dielectric time-dependent dielectric breakdown (TDDB), back-end-of-the-line (BEOL) reliability, Interconnect TDDB, electro-migration (EM), circuit reliability, packaging reliability, conventional and emerging memory reliability, failure analysis (FA), wafer-level reliability (WLR), among other topic are presented. The key focus areas at IIRW 2023 were Advanced node scaling solutions (FEOL/MOL/BEOL), circuit reliability (device-circuit degradation and aging).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"159-160"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Transactions on Device and Materials Reliability Publication Information IEEE 器件与材料可靠性期刊》出版信息

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405818

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Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers 半导体制造设计 (DFM) 特刊联合征稿

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3412348

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