A Novel Dual-Mode Dual Trench MOSFET With Self-Adjustable Field Plate for Low EMI Noise and High Dynamic Avalanche Robustness

IF 2.3 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-04-01 DOI:10.1109/TDMR.2025.3556015

Tongyang Wang;Zehong Li;Yishang Zhao;Ziming Xia;Yige Zheng;Jun Ye;Xuan Xiao

{"title":"A Novel Dual-Mode Dual Trench MOSFET With Self-Adjustable Field Plate for Low EMI Noise and High Dynamic Avalanche Robustness","authors":"Tongyang Wang;Zehong Li;Yishang Zhao;Ziming Xia;Yige Zheng;Jun Ye;Xuan Xiao","doi":"10.1109/TDMR.2025.3556015","DOIUrl":null,"url":null,"abstract":"A novel dual-mode dual trench MOSFET (DDT-MOSFET) featuring shorted P-doping field plate (PFP) and N-doping field plate (NFP) is proposed. A parasitic depletion region capacitor and a parasitic MOSFET are introduced in the self-adjustable field plate (SFP). During turn-on, the DDT-MOSFET is in the split gate trench (SGT) mode with an electron inversion layer in the PFP, achieving low <inline-formula> <tex-math>$C_{\\mathrm { gd}}$ </tex-math></inline-formula>. During turn-off, the DDT-MOSFET is in the insulator pillar superjunction (I-SJ) mode with depleted PFP, achieving low electromagnetic interference (EMI) noise and high breakdown voltage (BV). Mode conversion is realized by the introduction of the SFP. By TCAD simulation, during turn-off, the proposed structure exhibits 33.9% improvement in BV, 42.8% reduction in maximum <inline-formula> <tex-math>$dI_{\\mathrm { D}}$ </tex-math></inline-formula>/dt and 44.1% reduction in overshoot voltage <inline-formula> <tex-math>$(V_{\\mathrm { O}})$ </tex-math></inline-formula> with same <inline-formula> <tex-math>$E_{\\mathrm { off}}$ </tex-math></inline-formula>, reducing EMI noise and improving dynamic avalanche robustness without deterioration of other electrical characteristics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"274-280"},"PeriodicalIF":2.3000,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10945783/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

A novel dual-mode dual trench MOSFET (DDT-MOSFET) featuring shorted P-doping field plate (PFP) and N-doping field plate (NFP) is proposed. A parasitic depletion region capacitor and a parasitic MOSFET are introduced in the self-adjustable field plate (SFP). During turn-on, the DDT-MOSFET is in the split gate trench (SGT) mode with an electron inversion layer in the PFP, achieving low

$C_{\mathrm { gd}}$

. During turn-off, the DDT-MOSFET is in the insulator pillar superjunction (I-SJ) mode with depleted PFP, achieving low electromagnetic interference (EMI) noise and high breakdown voltage (BV). Mode conversion is realized by the introduction of the SFP. By TCAD simulation, during turn-off, the proposed structure exhibits 33.9% improvement in BV, 42.8% reduction in maximum

$dI_{\mathrm { D}}$

/dt and 44.1% reduction in overshoot voltage

$(V_{\mathrm { O}})$

with same

$E_{\mathrm { off}}$

, reducing EMI noise and improving dynamic avalanche robustness without deterioration of other electrical characteristics.

查看原文本刊更多论文

一种具有自调场极板的新型双模双沟槽MOSFET，具有低电磁干扰噪声和高动态雪崩鲁棒性

提出了一种新型的双模双沟槽MOSFET (DDT-MOSFET)，其特点是短接p掺杂场板（PFP）和n掺杂场板（NFP）。在自调场极板（SFP）中引入了寄生耗尽区电容和寄生MOSFET。在导通过程中，DDT-MOSFET处于分栅沟槽（SGT）模式，在PFP中有一个电子反转层，实现低$C_{\ mathm {gd}}$。在关断过程中，DDT-MOSFET处于绝缘子柱超结（I-SJ）模式，PFP耗尽，实现低电磁干扰（EMI）噪声和高击穿电压（BV）。模式转换是通过引入SFP实现的。通过TCAD仿真，该结构在关断过程中BV提高33.9%，最大dI_{\mathrm {D}}$ /dt降低42.8%，超调电压$(V_{\mathrm {O}})$降低44.1%，降低了电磁干扰噪声，提高了动态雪崩鲁棒性，同时不影响其他电气特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.