IEEE Transactions on Device and Materials Reliability最新文献

Call for Nominations for Editor-in-Chief IEEE Transactions on Semiconductor Manufacturing

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3535976

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Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29

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IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3551113

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IEEE Transactions on Device and Materials Reliability Information for Authors

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IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3549643

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Special Issue on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS 2023) in the IEEE Transactions on Device and Materials Reliability

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IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3544351

Luca Cassano;Mihalis Psarakis

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IEEE Transactions on Device and Materials Reliability Publication Information

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IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3549656

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Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications

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IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3551112

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Wide Band Gap Semiconductors for Automotive Applications

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IEEE Transactions on Device and Materials Reliability Pub Date : 2025-03-19 DOI: 10.1109/TDMR.2025.3551111

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FPGA Assessment Methodology of Adverse X-Ray Effects on Secure Digital Circuits

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-02-21 DOI: 10.1109/TDMR.2025.3538484

Nasr-Eddine Ouldei Tebina;Luc Salvo;Nacer-Eddine Zergainoh;Guillaume Hubert;Paolo Maistri

{"title":"FPGA Assessment Methodology of Adverse X-Ray Effects on Secure Digital Circuits","authors":"Nasr-Eddine Ouldei Tebina;Luc Salvo;Nacer-Eddine Zergainoh;Guillaume Hubert;Paolo Maistri","doi":"10.1109/TDMR.2025.3538484","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3538484","url":null,"abstract":"Recent research demonstrates the feasibility of X-ray attacks. Unlike traditional fault injection methods, X-rays offer precise spatial targeting because of their short wavelength and high penetration power. This allows attackers to selectively target specific regions within a device, from individual transistors to larger blocks. This necessitates a new perspective on hardening techniques, requiring designers to consider the impact of X-ray irradiation on both fault injection and power consumption. To address this challenge, the paper proposes a characterization flow that analyzes the differences in side-channel leakages of FPGA components and their susceptibility to increased leakage due to X-ray effects. Despite the fundamental differences between ASIC and FPGA layouts, they both share the characteristic of being MOS technology-based, which makes them both susceptible to TID effects. The simulation results strongly support the theory that X-rays can induce leakage currents, thereby amplifying the side-channel information leakage observed in our experiments on FPGAs. Furthermore, these results provide concrete evidence that different FPGA components exhibit varying susceptibility to X-ray-induced leakage. Our findings reveal a clear hierarchy of vulnerability, with interconnects being the most susceptible elements, followed by registers, and lastly, logic components (LUTs and MUXes). This differential vulnerability offers valuable information for designers of secure cryptographic circuits. By understanding how X-rays impact different components, hardening techniques can be strategically targeted to provide the most effective protection against both fault injection and side-channel leakage.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"85-94"},"PeriodicalIF":2.5,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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From Ground to Orbit: A Robust and Efficient Test Methodology for RISC-V Soft-Cores 从地面到轨道：RISC-V 软核的稳健高效测试方法

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-02-13 DOI: 10.1109/TDMR.2025.3537718

Bruno Forlin;Kevin Böhmer;Carlo Cazzaniga;Paolo Rech;Gianluca Furano;Nikolaos Alachiotis;Marco Ottavi

{"title":"From Ground to Orbit: A Robust and Efficient Test Methodology for RISC-V Soft-Cores","authors":"Bruno Forlin;Kevin Böhmer;Carlo Cazzaniga;Paolo Rech;Gianluca Furano;Nikolaos Alachiotis;Marco Ottavi","doi":"10.1109/TDMR.2025.3537718","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3537718","url":null,"abstract":"As traditional space-grade computing systems struggle to meet the increasing computational demands of modern space missions, RISC-V emerges as a promising alternative due to its open-source and highly customizable nature. However, the extensive hardware customization options in RISC-V introduce complexity in validation, making it challenging to ensure system reliability. This paper introduces a robust methodology for validating RISC-V-based systems under accelerated radiation beams, focusing on test uptime, leveraging Commercial Off-The-Shelf (COTS) FPGA devices, which offer flexibility and cost-effectiveness, to enable concurrent hardware and software development. We demonstrate how our methodology offers a comprehensive approach for testing heterogeneous systems on FPGAs, balancing thorough integration with cost-efficiency and test robustness. During our experiments with accelerated neutrons to assess the resilience of RISC-V cores, our approach guaranteed the correct delivery of 100% of the packages, while minimizing system downtime during radiation testing by reducing the Test Fixture SEFI cross-section.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"27-36"},"PeriodicalIF":2.5,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-01-23 DOI: 10.1109/TDMR.2025.3533004

Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma

{"title":"Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges","authors":"Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma","doi":"10.1109/TDMR.2025.3533004","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3533004","url":null,"abstract":"The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I<inline-formula> <tex-math>$_{text {ON}}$ </tex-math></inline-formula>) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V<inline-formula> <tex-math>$_{text {DS}} = 0.3$ </tex-math></inline-formula>V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"163-172"},"PeriodicalIF":2.5,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0