IEEE Transactions on Device and Materials Reliability最新文献

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3520737

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IEEE Transactions on Device and Materials Reliability Publication Information

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3516717

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IEEE Transactions on Device and Materials Reliability Information for Authors

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3516718

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TDMR December 2024 Editorial

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3508312

Edmundo Gutierrez

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3516719

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Editorial on EOS

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3507412

Ming-Dou Ker

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Call for Nominations for Editor-in-Chief

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-23 DOI: 10.1109/TDMR.2024.3513737

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Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-12 DOI: 10.1109/TDMR.2024.3496821

Aryan Kannaujiya;Shubham Singh;Ambika Prasad Shah;Daniele Rossi

{"title":"Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity","authors":"Aryan Kannaujiya;Shubham Singh;Ambika Prasad Shah;Daniele Rossi","doi":"10.1109/TDMR.2024.3496821","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3496821","url":null,"abstract":"This work presents enhanced hysteresis width for noise-immune radiation-hardened Schmitt trigger circuits. A dual-mode Domino-based Schmitt trigger (DST) circuit is employed for dual purposes owing to the inclusion of a control module that functions as both a domino logic and a Schmitt trigger circuit. For various ST circuits, key performance metrics including hysteresis width, power consumption, latency, process variation, and critical charge at sensitive nodes are determined. The findings demonstrate that, in comparison to other reference circuits, the DST has improved performance metrics. The proposed DST has \u0000<inline-formula> <tex-math>$3.89times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$1.58times $ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$1.03times $ </tex-math></inline-formula>\u0000 lower dynamic power, leakage power, and propagation delay, respectively in comparison to conventional ST. The hysteresis width of DST is \u0000<inline-formula> <tex-math>$1.32times $ </tex-math></inline-formula>\u0000 higher than conventional ST which makes it more practical for a noisy environment. All the simulation work has been handled by the Cadence virtuoso tool using UMC 40nm technology.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"602-609"},"PeriodicalIF":2.5,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Trap Location and Stress Degradation Analysis of GaN High Electron Mobility Transistors Based on the Transient Current Method

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-11 DOI: 10.1109/TDMR.2024.3495987

Qian Wen;Lixing Zhou;Xianwei Meng;Shiwei Feng;Yamin Zhang

{"title":"Trap Location and Stress Degradation Analysis of GaN High Electron Mobility Transistors Based on the Transient Current Method","authors":"Qian Wen;Lixing Zhou;Xianwei Meng;Shiwei Feng;Yamin Zhang","doi":"10.1109/TDMR.2024.3495987","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3495987","url":null,"abstract":"In this paper, the carrier trapping behavior and electrical characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) under different bias conditions are studied based on the transient current. By considering the transient drain current of HEMTs at different temperatures, three trapping mechanisms are identified: (1) charge trapping in the AlGaN barrier layer, in the gate-drain region near the two-dimensional electron gas (2DEG) channel; (2) charge trapping in the GaN layer, in the gate-drain region near the gate; and (3) charge trapping on the surface of the AlGaN layer, in the gate-drain region near the gate. The influences of the source-gate and drain-gate voltages on trapping behavior are analyzed to further elucidate the trap locations. The experimental results show that charge capture is mainly affected by the drain-gate voltage. High electric field stress affects the local structure order inside the device, thus affecting the charge escape rate. The threshold voltage shift is mainly affected by the surface trap of the AlGaN layer near the gate.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"624-630"},"PeriodicalIF":2.5,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-01 DOI: 10.1109/TDMR.2024.3488750

Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky

{"title":"Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform","authors":"Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky","doi":"10.1109/TDMR.2024.3488750","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3488750","url":null,"abstract":"As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"637-645"},"PeriodicalIF":2.5,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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