IEEE Transactions on Device and Materials Reliability最新文献

{"title":"An Improved Steep-Slope Triple Metal Gate-Dual Dielectric-GaAs-Pocket-HTFET With Interface Trap Charges Analysis","authors":"Madhulika Verma;Ankita Singh;Sachin Agrawal","doi":"10.1109/TDMR.2025.3595573","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3595573","url":null,"abstract":"This article presents a Triple Metal Gate-Dual Dielectric-GaAs Pocket-Heterojunction Tunnel Field Effect Transistor (TMG-DD-GaAs-pocket-HTFET) for low-power and high-speed applications. To enhance carrier confinement and suppress ambipolar current, the device integrates triple gates (M1, M2, and M3) with a dual-dielectric stack of HfO2/SiO2 on a single layer. Additionally, SiGe is utilized as the source material to improve tunneling efficiency, while GaAs is employed as the pocket material to enhance carrier injection and overall device performance. The device’s characteristics are investigated using the Silvaco-TCAD simulator, focusing on its switching behavior and subthreshold performance. Further, the device’s immunity under interface trap charge (ITC) like positive (P-ITC), negative (N-ITC), and without interface trap charge (W-ITC) conditions is investigated. At a gate and drain voltage of 0.5 V, the W-ITC configuration achieves a low threshold voltage (Vth) of 0.19 V, an ultra-low subthreshold swing (SS) of 2.53 mV/decade, and a high ION of <inline-formula> <tex-math>$5.83times 10{^{text {-5}}}$ </tex-math></inline-formula> A, with an exceptional ION/IOFF ratio of <inline-formula> <tex-math>$1.42times 10{^{{12}}}$ </tex-math></inline-formula>. The results show that the device’s performance is unaffected by the presence of positive or negative interface trap charges. These findings ensured that the proposed TMG-DD-GaAs-pocket-HTFET is a highly promising option for low-power, high-speed applications, with excellent scalability and enhanced performance. Key analog/RF parameters, including transconductance <inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula>, gate capacitance (<inline-formula> <tex-math>$C_{gd}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$C_{gs}$ </tex-math></inline-formula>), cut-off frequency <inline-formula> <tex-math>$(f_{T})$ </tex-math></inline-formula>, transconductance frequency product (TFP), and gain-bandwidth product (GBP), have been calculated. Additionally, an in-depth analysis under W-ITC condition is performed to assess the impact of varying gate work functions, gate lengths, and pocket materials on the device’s performance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"668-676"},"PeriodicalIF":2.3,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on Electrostatic Discharge and Surge Robustness of Silicon Carbide High-Voltage Devices","authors":"Ya-Zhi Hu;Ming-Dou Ker","doi":"10.1109/TDMR.2025.3594470","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3594470","url":null,"abstract":"This work presents a comprehensive study on the electrostatic discharge (ESD) and surge robustness of 4H-SiC vertical double-implanted MOSFETs (VDMOSFETs). The ESD analysis includes human-body-model (HBM) and transmission-line-pulse (TLP) testing across various stress modes, complemented by transient waveform measurements and TCAD simulations. The surge analysis also introduces the transient analysis and TCAD simulation. Both single and repetitive surge stress surge tests are conducted to evaluate electrical degradation behavior. In both HBM ESD and surge tests, GS and –DG modes are vulnerable to gate oxide breakdown. Physical failure analysis techniques, including Optical Beam Induced Resistance Change (OBIRCH), Scanning Electron Microscopy (SEM), and Focused Ion Beam (FIB) techniques, are used to identify damage locations and failure mechanisms of the failure samples.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"601-609"},"PeriodicalIF":2.3,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Single-Event Burnout in 4H-SiC Avalanche Photodiode","authors":"Wang-Zi-Xuan Zhen;Zhong-Qing Zhang;Cheng-Hao Yu;Hao-Min Guo;Masayuki Yamamoto;Da-Wei Wang;Bing Hong;Chun-Sheng Jiang;Wen-Sheng Zhao","doi":"10.1109/TDMR.2025.3593916","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3593916","url":null,"abstract":"This paper presents the 2-D numerical simulation results of the heavy-ion-induced single-event leakage current (SELC) degradation and single-event burnout (SEB) in the silicon-carbide (SiC) avalanche photodiode (APD). The employed simulation physics models and material parameters are validated by the reverse I-V characteristics and spectral response characteristics in experiments. The region most sensitive to heavy ion is identified. Then, the SEB failure behavior of SiC APD is investigated. Based on the analysis of ion-induced SELC degradation or SEB failure, three hardening methods–modifying the mesa etch depth, introducing Low Carrier Lifetime Control (LCLC) region, and inserting buffer layer–are investigated. As a result, the effects of three hardening methods on the electrical properties and SEB performance for SiC APD are compared.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"430-440"},"PeriodicalIF":2.3,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of BTI Lifetime for MOSFETs in 55 nm CMOS Node by 1/f Noise Performance Degradation","authors":"Yi Jiang;Yanning Chen;Rui Su;Fang Liu;Bo Wu;Yongfeng Deng;Dawei Gao;Junkang Li;Rui Zhang","doi":"10.1109/TDMR.2025.3593375","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3593375","url":null,"abstract":"In this study, the bias temperature instability (BTI) degradation of Si p- and n-MOSFETs fabricated using a 55 nm CMOS process was systematically and quantitatively investigated over stress time <inline-formula> <tex-math>$(T_{stress})$ </tex-math></inline-formula>. This analysis focused on key parameters, including threshold voltage shift <inline-formula> <tex-math>$(Delta V_{th})$ </tex-math></inline-formula>, subthreshold swing degradation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>SS), maximum transconductance reduction (<inline-formula> <tex-math>$Delta Gm_{max}$ </tex-math></inline-formula>), linear region current decrease <inline-formula> <tex-math>$(Delta I_{dlin})$ </tex-math></inline-formula>, and 1/f noise performance degradation. By examining the dependence of these parameters on <inline-formula> <tex-math>$T_{stress}$ </tex-math></inline-formula>, the corresponding BTI lifetime under weak BTI stress was evaluated. It was found that assessing BTI lifetime via 1/f noise required only 35 s and 50 s for Si p- and n-MOSFETs, respectively. Furthermore, comparing the predicted lifetime derived from degradation data at various <inline-formula> <tex-math>$T_{stress}$ </tex-math></inline-formula> with the actual BTI lifetimes (2550 s for p-MOSFETs and 2200 s for n-MOSFETs), the 1/f noise method emerged as the fastest and most accurate approach. This is attributed to its superior linearity and degradation amplitude over <inline-formula> <tex-math>$T_{stress}$ </tex-math></inline-formula> on log-log scale. These findings contribute to proposing a novel method for obtaining the BTI lifetime of MOSFETs regarding the 1/f noise degradation, particularly for analog/mixed-signal (AMS) and radio frequency (RF) applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"424-429"},"PeriodicalIF":2.3,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lifetime Prediction Method for IGBT Modules Under Combined Power Cycling–Vibration Conditions","authors":"Rui Zhou;Tong An;Fei Qin","doi":"10.1109/TDMR.2025.3592624","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3592624","url":null,"abstract":"Certain insulated gate bipolar transistor (IGBT) modules, such as automotive-grade IGBT modules, are often subjected to harsh service environments. Generally, two factors, temperature variation and vibration, exist simultaneously. Under the combined effects of thermal stress and dynamic mechanical stress, the process of crack extension in Al bonding wires accelerates, leading to the premature failure of IGBT modules. However, little is known about the lifetime prediction method that can be used for IGBT modules under combined power cycling–vibration loading conditions. First, this paper establishes a lifetime prediction method that is applicable for predicting the lifetime of IGBT modules under power cycling conditions; this method includes a power loss model, an RC thermal network model and a collector–emitter on-resistance <inline-formula> <tex-math>$(r_{mathrm { ce}})$ </tex-math></inline-formula> degradation model. Then, the effect of vibration on the lifetime of the IGBT module is considered in the lifetime prediction method by equating the vibration stress with the thermal stress via finite element (FE) analysis. The method considers the service conditions under combined power cycling–vibration conditions and the self-acceleration effect of Al bond wire damage accumulation on the lifetime of IGBT modules. Using comparisons with experimental results, it is verified that the lifetime prediction method can accurately and efficiently predict the life of an IGBT module under both power cycling conditions and combined power cycling–vibration conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"714-722"},"PeriodicalIF":2.3,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DCGAN-Driven Minority Class Augmentation for Lightweight YOLO-Based Photovoltaic Defect Localization Suitable for Edge Deployment","authors":"Nakka Saampotth Maddileti;Rupesh Namburi;Rayappa David Amar Raj;Rama Muni Reddy Yanamala;Archana Pallakonda","doi":"10.1109/TDMR.2025.3592416","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3592416","url":null,"abstract":"This study presents YOLOv11n-GhostLite, an innovative lightweight deep learning architecture optimized for real-time localization of photovoltaic (PV) faults in electroluminescence (EL) images, specifically designed for edge deployment. A Deep Convolutional Generative Adversarial Network (DCGAN)-based synthetic augmentation pipeline is presented to address the issues of class imbalance and limited resource availability, generating high-fidelity, class-conditional EL images that include realistic banding artifacts. This method enhances the representation of minority defect categories by more than 150%, elevating the mean Average Precision (mAP@50) by 4% and decreasing false negatives by 5%. The proposed model incorporates GhostConv for efficient early feature extraction, C3k2 residual blocks for deep representation learning, GhostSPPF for multi-scale context aggregation, C2PSA attention for adaptive feature refinement, and an anchor-free detection head, achieving high performance with only 2.34 million parameters and 6.2 GFLOPs. Detailed experiments on two benchmark datasets PVEL-AD and PV Multi-Defect exhibit the model’s efficacy, attaining 97.2% mAP@50 on PVEL-AD, and 96.4% mAP@50 on PV Multi-Defect, outperforming larger models in both accuracy and speed. The model is further deployed on a Google Coral Edge TPU, demonstrating its real-time functionality with minimal power consumption (~2W) and suitable latency for drone-based solar inspections. YOLOv11n-GhostLite’s integration of efficient architecture and data-driven augmentation renders it an effective solution for scalable, real-time photovoltaic fault detection in resource-limited settings.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"742-751"},"PeriodicalIF":2.3,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Single Event Irradiation-Hardened SOI Trench Gate LIGBT","authors":"Weidan Li;Mingmin Huang;Min Gong","doi":"10.1109/TDMR.2025.3590736","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3590736","url":null,"abstract":"A trench gate lateral insulated gate bipolar transistor with an extra hole path (HP LIGBT) is proposed to ease the current concentration around the trench gate so as to suppress single-event burnout (SEB) and reduce the maximum electric field at the gate oxide so as to lower the risk of single-event gate rupture (SEGR). The SEB position of the trench gate LIGBT in comparison with the trench gate laterally diffused metal-oxide semiconductor (LDMOS) is studied by TCAD simulations with lattice heating model, where the former fails around the trench gate but the latter fails at the drain contact. The most sensitive position for inducing SEB is found to be both at the n-drift region near the emitter or source side. Simulation results show that the threshold voltage of triggering SEB of the HP LIGBT for ion species with high linear energy transfer (LET) values of 76.56 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg can be 46% higher than that of the conventional LIGBT. Moreover, the maximum electric field at the gate oxide of HP LIGBT is 55% lower than the conventional LIGBT.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"692-697"},"PeriodicalIF":2.3,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation Analysis of 14 nm SOI FinFETs by Influence of Hot Carrier Injection and Self-Heating Synergistic Effects","authors":"Zhaohui Qin;Lei Dong;Lan Chen;Renjie Lu;Rong Chen;Yali Wang","doi":"10.1109/TDMR.2025.3590371","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3590371","url":null,"abstract":"With device dimensions shrink, traditional plane-field effect transistors no longer meet the demands of the development. As a novel type of three-dimensional device, 14 nm SOI FinFETs has been widely research attention and application due to the superior performance. However, Hot Carrier Injection (HCI) at different temperatures and its synergistic effect with Self-Heating Effect (SHE) synergistic effects have serious effects on the reliability of 14 nm SOI FinFETs and need to be solved. Therefore, this work uses Technology Computer-Aided Design to explore the electrical performance degradation of the 14 nm SOI FinFETs to reveal the damage mechanism. Simulation results demonstrate the threshold voltage shift and electron mobility decrease of the device. The increase in ambient temperature and the rise in lattice temperature induced by SHE will exacerbate the HCI effect, resulting in more hot charge carriers being injected into the gate oxide layer. Based on results, achieving more efficient thermal management by enhancing the heat dissipation performance of the drain and its extended regions can provide important theoretical support for reliability design.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"659-667"},"PeriodicalIF":2.3,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exponential Gain Degradation Behavior on Irradiated InP/InGaAs Double Heterojunction Bipolar Transistors","authors":"Jialin Zhang;Yongbo Su;Bo Mei;Feng Yang;Zhi Jin;Yinghui Zhong","doi":"10.1109/TDMR.2025.3590272","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3590272","url":null,"abstract":"In this paper, the effects of 2 MeV-proton irradiation on the electrical characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) are investigated. The device characteristics suddenly degraded for proton fluences exceeding <inline-formula> <tex-math>$1times 10{^{{13}}}$ </tex-math></inline-formula> cm−2 and almost functionally failed for proton fluences reaches <inline-formula> <tex-math>$1times 10{^{{14}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-}2 $ </tex-math></inline-formula>. The increase in base current is directly responsible for the degradation of current gain. It was demonstrated that the reciprocal gain of irradiated InP/InGaAs DHBTs exhibits an exponential relationship with proton fluence over a broader fluence range below <inline-formula> <tex-math>$5times 10{^{{13}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-}2 $ </tex-math></inline-formula>, rather than a linear relationship as described by the Messenger-Spratt equation. The analysis of base current components and micro-Raman spectrums indicates that the electrostatic-potential modulation effect of irradiated defects as charged centers on the BE junction is the main cause of gain degradation. Furthermore, a comparison with irradiation effects of other bipolar transistors enhances our understanding of the varied impact of radiation-induced defects on the gain degradation across different transistor architectures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"452-459"},"PeriodicalIF":2.3,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comprehensive Modeling Framework for Charge-Sharing and Bias-Dependent Single Event Transient Prediction in FinFETs","authors":"Wangyong Chen;Zhengxin Zhang;Jianwen Lin;Linlin Cai","doi":"10.1109/TDMR.2025.3589784","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3589784","url":null,"abstract":"With the scaling of integrated circuit technologies, charge-sharing effects induced by single-event transient (SET) have become a critical reliability concern in radiation environments. However, conventional circuit-level SET simulation methodologies fail to account for charge-sharing mechanisms among adjacent devices. This work proposes a physics-aware simulation framework combining technology computer-aided design (TCAD) device simulations and circuit-level modeling to address this limitation. The methodology involves extracting transient current waveform parameters through 3D TCAD simulations under varied ion strike locations. Spatially-dependent behavioral models are then developed via multivariate regression of these parameters, which are subsequently integrated into bias-dependent SET analytical models. To enable circuit-level analysis, built-in current sources characterized by the developed models are inserted at sensitive nodes during layout-aware simulations. The proposed approach is validated through comparative analysis between TCAD mixed-mode simulations and circuit-level predictions in a 12-nm FinFET test structure, demonstrating smaller deviation in critical SET metrics. Compared to existing methods, this co-simulation strategy incorporates both charge-sharing effects and bias voltage dependencies while maintaining computational efficiency. The implemented framework enables early-stage evaluation of radiation-induced soft errors during physical design phases, providing critical insights for radiation-hardened-by-design strategies in advanced process nodes.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"520-527"},"PeriodicalIF":2.3,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}