IEEE Transactions on Device and Materials Reliability最新文献_第2页

Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform 总电离剂量对新兴垂直背栅CMOS平台DC/RF性能的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-01 DOI: 10.1109/TDMR.2024.3488750

Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky

{"title":"Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform","authors":"Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky","doi":"10.1109/TDMR.2024.3488750","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3488750","url":null,"abstract":"As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"637-645"},"PeriodicalIF":2.5,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study on Electromagnetic Pulse Damage of 22nm FDSOI in Radiation Environment 22nm FDSOI在辐射环境中的电磁脉冲损伤研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-23 DOI: 10.1109/TDMR.2024.3485095

Chen Chong;Xing Li;Hongxia Liu;Wei Zhou;Menghao Huang

引用次数: 0

Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress 极高栅极电压应力下SiC mosfet栅氧化可靠性评估

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-18 DOI: 10.1109/TDMR.2024.3478220

Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang

引用次数: 0

Analysis of Thermal Expansion Behavior and Interface Evolution of TSV Under Thermal Cycle Loading Based on Crystal Plastic Finite Element Method 基于晶体塑性有限元法的TSV热循环载荷下热膨胀行为及界面演化分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-10 DOI: 10.1109/TDMR.2024.3478183

Kaihong Hou;Zhengwei Fan;Xun Chen;Shufeng Zhang;Yashun Wang;Yu Jiang

引用次数: 0

Investigating the Arc-Shaped Kink Drain Voltage of Drain Current With Capacitance-Voltage Measurement Method in GaN HEMTs 用电容电压测量法研究GaN hemt中漏极电流的弧形结漏极电压

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-30 DOI: 10.1109/TDMR.2024.3467344

Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang

{"title":"Investigating the Arc-Shaped Kink Drain Voltage of Drain Current With Capacitance-Voltage Measurement Method in GaN HEMTs","authors":"Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang","doi":"10.1109/TDMR.2024.3467344","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467344","url":null,"abstract":"In this study, the measure-stress-measure (MSM) technique under the arc-shaped kink drain voltage (VD,kink) conditions is applied to investigate the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 in GaN high electron mobility transistors (HEMTs). Forward and reverse transfer curves indicate that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 would change with gate voltages increasing. However, no previous study has investigated the exact location of traps that would dominate the loci of VD,kink. The results suggest that the trend of on-state current (Ion) degradation is caused by threshold voltage (Vt) shift. Hence, it can be determined that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 is related to the degree of impact ionization, which is dominant by the holes generation in the buffer. In addition, the capacitance-voltage (C-V) measurements reveal that holes generated through impact ionization at the gate edge are responsible for the shift in VD,kink. This physical mechanism is further supported by temperature-dependent analysis. Finally, the results offer a novel C-V measurement to characterize and model the physical mechanisms of the kink effect, which is governed by hot carrier degradation in GaN HEMTs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"544-548"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Switching Characteristics Degradation of GaN HEMT Under Power Cycling Aging 功率循环老化下GaN HEMT开关特性退化研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-30 DOI: 10.1109/TDMR.2024.3468013

Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han

{"title":"Investigation of Switching Characteristics Degradation of GaN HEMT Under Power Cycling Aging","authors":"Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han","doi":"10.1109/TDMR.2024.3468013","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468013","url":null,"abstract":"GaN HEMT devices have wide application prospects because of their high electron mobility and excellent electrical characteristics. However, due to the lack of reliability analysis of the switching characteristics, GaN HEMT devices are unable to realize their maximum potential in practical applications. In this paper, GaN HEMT devices are aged based on power cycling. The switching degradation behavior of GaN HEMT devices after aging is characterized by double pulse test. The test results show that the switching delay increases, the Miller platform lengthens, and the opening ringing decreases after power cycle aging. In order to explore the degradation mechanism, the effects of parasitic capacitance on the switching characteristics are characterized by double pulse test of parallel capacitors. Based on the analysis of the parasitic capacitance model, the degradation trend of each parasitic capacitance caused by trap after aging is deduced and verified by experiment. The results show that the trap increase of AlGaN layer caused by inverse piezoelectric effect and hot-electron effect is the main reason for the change of parasitic capacitance after aging, while the on-state and off-state capacitance of GaN HEMT devices have completely different composition mechanism and change trends, which lead to different trends and degrees of degradation of each switching characteristic. This can provide a valuable reference for the reliability of GaN HEMT devices in long-term applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"610-617"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A SiC Trench Schottky Diode With Accelerated Hole Extraction and Recombination Structure for Enhancing Single-Event Burnout Tolerance 一种具有加速孔提取和复合结构的碳化硅沟槽肖特基二极管，用于提高单事件灼烧容忍度

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-26 DOI: 10.1109/TDMR.2024.3468468

Rui Yang;Xiaochuan Deng;Haibo Wu;Xu Li;Xuan Li;Song Bai;Yi Wen;Bo Zhang

{"title":"A SiC Trench Schottky Diode With Accelerated Hole Extraction and Recombination Structure for Enhancing Single-Event Burnout Tolerance","authors":"Rui Yang;Xiaochuan Deng;Haibo Wu;Xu Li;Xuan Li;Song Bai;Yi Wen;Bo Zhang","doi":"10.1109/TDMR.2024.3468468","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468468","url":null,"abstract":"A SiC trench junction barrier Schottky diode with multiple P-shield layers and an embedded N+ region (MPNT-JBS) is proposed and investigated for enhancing single-event burnout (SEB) tolerance. The Schottky contact at the sidewall of the trench and the embedded N+ region in MPNT-JBS accelerate the extraction and recombination of holes. The mitigated accumulation of holes contributes to the reduction of the strong electric field near the metal/SiC interface, thus favoring a decrease in the high temperature. Under 50% of the rated voltage (\u0000<inline-formula> <tex-math>$V_{mathrm { Cathode}}{=}600$ </tex-math></inline-formula>\u0000 V), the maximum temperature near the metal/SiC interface in MPNT-JBS decreases by 78% and 71% compared to SiC JBS diode with multilayer N-buffer (MB-JBS), corresponding to the instances when heavy ions with a linear energy transfer (LET) value of 0.53 pC/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m strike the middle of the Schottky contact and the P+ region, respectively. In addition, the multilayer P-shield of MPNT-JBS suppresses the peak temperature near the PN junction by enlarging the energy dissipation area and lowering the transient heat power near the PN junction. Compared to MB-JBS, the maximum temperature near the PN junction in MPNT-JBS decreases from 1890 K to 1454 K when heavy ions strike the middle of the P+ region (\u0000<inline-formula> <tex-math>$V_{mathrm { Cathode}}{=}600$ </tex-math></inline-formula>\u0000 V). These results indicate that MPNT-JBS provides potential for enhancing SEB tolerance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"549-555"},"PeriodicalIF":2.5,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication 重复热应力法在CMOS工艺中氘钝化的研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-25 DOI: 10.1109/TDMR.2024.3467249

Ju-Won Yeon;Sung-Su Yoon;Hyo-Jun Park;Tae-Hyun Kil;Dong-Hyun Wang;Khwang-Sun Lee;Dae-Han Jung;Ja-Yun Ku;Jun-Young Park

{"title":"Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication","authors":"Ju-Won Yeon;Sung-Su Yoon;Hyo-Jun Park;Tae-Hyun Kil;Dong-Hyun Wang;Khwang-Sun Lee;Dae-Han Jung;Ja-Yun Ku;Jun-Young Park","doi":"10.1109/TDMR.2024.3467249","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467249","url":null,"abstract":"High-pressure deuterium annealing (HPDA) has been proposed as a promising process to enhance device performance and reliability. However, additional thermal stress after the HPDA can lead to de-passivation of Si-D bonds at the gate dielectric interface. In this study, electrical characterization of deuterium annealed MOSFETs after repetitive thermal stress conditions is performed to obtain guidelines for conducting post-metal annealing. MOSFETs are fabricated on silicon wafer to verify the passivation as well as de-passivation of deuterium. Device parameters including subthreshold swing (SS), on-state current \u0000<inline-formula> <tex-math>$(I_{mathrm { ON}})$ </tex-math></inline-formula>\u0000, off-state current \u0000<inline-formula> <tex-math>$(I_{mathrm { OFF}})$ </tex-math></inline-formula>\u0000, and gate leakage \u0000<inline-formula> <tex-math>$(I_{mathrm { G}})$ </tex-math></inline-formula>\u0000, are comprehensively compared. Finally, hot-carrier injection (HCI) stress is applied to compare the changes in stress immunity resulting from deuterium de-passivation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"618-623"},"PeriodicalIF":2.5,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Failure Mechanism of Internal Circuit During ESD Striking a Power to Another Power ESD对电源冲击时内部电路的失效机理

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-24 DOI: 10.1109/TDMR.2024.3467116

Chih-Cherng Liao;Ching-Ho Li;Karuna Nidhi;Chieh-Yao Chuang;Hsien-Feng Liao;Yeh-Ning Jou;Ke-Horng Chen;Jian-Hsing Lee

引用次数: 0

Comparative Analysis of SGTMOS Degradation Under Repeated Off-State Avalanche and Short Circuit Current Pulses 重复断态雪崩和短路电流脉冲下SGTMOS退化的比较分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-24 DOI: 10.1109/TDMR.2024.3467096

Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang

{"title":"Comparative Analysis of SGTMOS Degradation Under Repeated Off-State Avalanche and Short Circuit Current Pulses","authors":"Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang","doi":"10.1109/TDMR.2024.3467096","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467096","url":null,"abstract":"In this article, a 60-V split-gate trench vertical double diffused metal-oxide-semiconductor field-effect transistor (SGTVDMOS, SGTMOS) with low on-resistance is designed and manufactured. The device adopts an ultra-deep split gate trench with a grounded bottom shield gate. The electrical parameters degradations subsequent to repeated off-state avalanche and short circuit current pulses are investigated and compared for the first time. After avalanche voltage stress, crucial parameters such as threshold voltage (Vt), Miller capacitance (CGD) remain unaffected. However, a noteworthy change is observed in blocking characteristics, manifested as an increase in breakdown voltage. Conversely, after subjecting the device to short-circuit pulse current stress, a minor reduction in \u0000<inline-formula> <tex-math>$rm V_{t}$ </tex-math></inline-formula>\u0000 is noted, while the breakdown characteristics remain constant. Technology computer-aided design (TCAD) simulation and actual test analysis are combined to reveal the degradation mechanism, it has been determined that electron injection degradation occurs under both stresses. However, distinct degradation phenomena occur due to the disparate positions of electron injection. During avalanche stress, electrons within the polysilicon (shield gate) tunnel into the oxide layer of the bottom shielding gate, while hot electron injection occurs near the active trench gate during a continuous short-circuit pulses.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"596-601"},"PeriodicalIF":2.5,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0