Radiation Hardened SOI LDMOS With Dual P-Type Layers Shielding Irradiation Charge Field

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-27 DOI:10.1109/TDMR.2024.3523577

Xin Zhou;Jie Shen;Ziqiu Tong;Zhao Qi;Ming Qiao;Zhaoji Li;Bo Zhang

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引用次数: 0

Abstract

In this paper, a novel radiation hardened SOI LDMOS with dual P-type layers is proposed. Based on irradiation charge field modulation, two P-type layers are introduced at the surface and bottom in N-drift region for suppressing shifts of both specific on-resistance

$(R_{\textrm {on,sp}})$

and breakdown voltage (BV). Irradiation charge field is shielded by the P-type layers at low drain voltage and electron behavior in the bulk is protected against the modulation, resulting in

$R_{\textrm {on,sp}}$

shifting less significantly. Besides, net charge density in drift region is reduced by the P-type layers, and then surface electric field is weakened at source side, resulting in a non-monotonic shift in BV. A low net charge density with high donor doping concentration in P-N-P drift region is pursued instead of charge balance required in traditional design. Simulated optimized results show that

$R_{\textrm {on,sp}}$

shifts only 11.4% at TID

${=} 300$

krad(Si).

查看原文本刊更多论文

双p型层屏蔽辐照电荷场的辐射硬化SOI LDMOS

本文提出了一种具有双p型层的新型抗辐射SOI LDMOS。基于辐照电荷场调制，在n漂移区表面和底部引入了两个p型层，以抑制比导通电阻$(R_{\textrm {on,sp}})$和击穿电压（BV）的位移。在低漏极电压下，p型层屏蔽了辐照电荷场，保护了体中的电子行为不受调制的影响，使得$R_{\textrm {on,sp}}$的位移不明显。此外，p型层降低了漂移区的净电荷密度，从而使源侧的表面电场减弱，导致BV发生非单调位移。在P-N-P漂移区追求低净电荷密度和高给体掺杂浓度，而不是传统设计所要求的电荷平衡。模拟优化结果表明，当TID ${=} 300$ krad（Si）时，$R_{\textrm {on,sp}}$偏移量仅为11.4%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.