IEEE Transactions on Device and Materials Reliability最新文献

{"title":"On the Reliability of Complementary Field Effect Transistor: Unveiling the Role of Grain Granularities and Random Fluctuations","authors":"Sandeep Kumar;Deven H Patil;Sunil Rathore;Ankit Dixit;Naveen Kumar;Vihar Georgiev;S. Dasgupta;Navjeet Bagga","doi":"10.1109/TDMR.2026.3665263","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3665263","url":null,"abstract":"This study presents a comprehensive statistical reliability analysis of monolithic Complementary Field Effect Transistors (CFETs), focusing on the impact of process-induced variations. The analysis highlights key sources of variability, including Metal Gate Granularity (MGG), Poly Grain Granularity (PGG), Random Dopant Fluctuation (RDF), and Line Edge Roughness (LER). In smaller geometries, the gate metal (or poly-gate) grain granularities play a significant role in threshold voltage (V<inline-formula> <tex-math>${}_{mathrm {th}}$ </tex-math></inline-formula>) variations, raising severe reliability concerns. Through calibrated statistical TCAD simulations, the ON current (I<inline-formula> <tex-math>${}_{mathrm {ON}}$ </tex-math></inline-formula>) variation of <inline-formula> <tex-math>$2.82~mu $ </tex-math></inline-formula>A (<inline-formula> <tex-math>$2.85~mu $ </tex-math></inline-formula>A) is observed in the nFET (pFET) side of CFET, due to MGG for experimentally reported 5 nm grain size. In advanced technologies like high bandwidth memory (HBM), the gate is made of polysilicon that suffers from the PGG in sub-3 nm node devices. The observed coefficient-of-variance (CV) of pFET (2.19) is higher than nFET (1.45), which shows higher variability in pFET due to poly grain size variations. Further, the process-induced RDF and LER significantly alter the V_th. Random numbers are generated by doping atoms in the Voronoi volume of each vertex to quantify the undoped and doped channels to statistically analyze the RDF. In contrast to a doped channel with <inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>V_th of 9 mV (7 mV) for nFET (pFET), the undoped scenario yields a default standard deviation (<inline-formula> <tex-math>$sigma $ </tex-math></inline-formula>V<inline-formula> <tex-math>${}_{mathrm {th}}$ </tex-math></inline-formula>) of 2 mV. To characterize LER, correlation length (<inline-formula> <tex-math>$Lambda $ </tex-math></inline-formula>) is a prime factor; as <inline-formula> <tex-math>$Lambda $ </tex-math></inline-formula> approaches the sheet width, CV increases by 24.32% (37.22%) in nFET (pFET). Thus, the results underscore the need for stringent control over grain morphology, doping precision, and edge definition to ensure reliable CFET performance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"365-371"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synergistic Impact of Total Ionizing Dose and Hot Carrier Effects on Modified and Unmodified Partially Depleted SOI P-MOSFETs","authors":"Qing Liu;Haomiao Cheng;Dawei Bi;Zhiyuan Hu;Zhengxuan Zhang;Sichang Zou","doi":"10.1109/TDMR.2025.3644177","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3644177","url":null,"abstract":"The synergistic effects of total ionizing dose (TID) and hot carrier injection (HCI) on silicon ion-implanted and unmodified partially depleted silicon-on-insulator (PDSOI) pMOSFETs are investigated. Both the TID and HCI effects in PMOS devices involve charge trapping and the creation of interface states. The experimental results show that there is mutual promotion or inhibition between them, depending on the sequence of irradiation and HCI stress, as well as the bias condition of the HCI stress. Theoretical analysis and simulation results demonstrate that the charges in the buried oxide layer not only affect the electric field distribution within the buried oxide but also influence the front gate, further affecting the irradiation and hot carrier degradation process.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"59-66"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterizing Threshold Voltage Drift of BTI Stress in SiC MOSFET From First-Principle Calculations","authors":"Guibao Wang;Pudong Wan;Miao Yu;Tiqiang Pang;Zihan Zhang;Yuming Zhang;Bo Peng;Lei Yuan;Renxu Jia","doi":"10.1109/TDMR.2026.3659921","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3659921","url":null,"abstract":"This study integrates experiments and density functional theory (DFT) to unravel atomic mechanisms of threshold voltage drift (<inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula>) in SiC MOSFETs under bias temperature instability (BTI). Direct current (DC)-BTI tests show polarity-dependent <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> (positive/negative shifts under ±gate bias), while alternating current (AC)-BTI yields persistent positive <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> under high stress. Based on the experimental observations, this work establishes four defect models for SiC MOS devices. Among them, the O₂-C=C-O₂, Si₂-C=C-Si₂, and V_O defects exhibit a higher electron trapping rate than the hole detrapping rate under positive bias conditions, accounting for the positive <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> observed during PBTI experiments. In contrast, the N_Si defect demonstrates a higher hole trapping rate than its electron detrapping rate, explaining the negative <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> in NBTI experiments. This behavior elucidates both positive and negative <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> under DC-BTI stress. Furthermore, the ratio between electron and hole charge transfer rates for the O₂-C=C-O₂, Si₂-C=C-Si₂, and V_O defects are more pronounced than that of the N_Si defect, confirming the positive <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> observed under AC-BTI stress. These defect-mediated dynamics establish a quantitative model linking atomic-scale charge imbalances to reliability degradation in wide-bandgap devices, highlighting defect engineering as critical for mitigating <inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula> instability in power electronics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"178-183"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Gate Reliability and Breakdown Voltage p-GaN HEMTs Based on Post-Annealing-Free Oxygen Plasma Treatment","authors":"Zifeng Qu;Jiachen Duan;Ang Li;Xuanming Zhang;Hao Tian;Jingyue Wu;Qiyi Guo;Qiyuan Zhang;Yizhou Jiang;Ningyu Luo;Xiaodong Zhang;Guohao Yu;Chao Long;Wen Liu;Huiqing Wen","doi":"10.1109/TDMR.2025.3638870","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3638870","url":null,"abstract":"This work presents an enhancement-mode (E-mode) p-GaN HEMT that significantly improves gate reliability and breakdown voltage through a post-annealing-free oxygen plasma treatment (GOPT). This method forms a GaOxN1−x interfacial layer beneath the gate metal, increasing the gate breakdown voltage from 13.8 V to 24.8 V and reducing the gate leakage current by three orders of magnitude at <inline-formula> <tex-math>$V_{mathrm {GS}} {=}8$ </tex-math></inline-formula> V, compared to conventional Schottky p-GaN gates. Time-dependent gate breakdown (TDGB) testing predicts a maximum safe operating gate voltage of 9.2 V for a 10-year lifetime with a 63% failure probability. The fabricated GOPT p-GaN HEMTs show excellent off-state drain breakdown performance, with a voltage of up to 2940 V at a gate-to-drain distance of <inline-formula> <tex-math>$28~{mu }$ </tex-math></inline-formula> m. This approach offers a simplified fabrication process with superior performance in both gate reliability and high-voltage capability, establishing GOPT p-GaN HEMTs as a promising candidate for high-performance, high-reliability power electronics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"277-282"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bypass Diode Performance Analysis and Improvement for Enhanced Electrothermal Response of PV Arrays","authors":"Kashika Baranwal;Prem Prakash;Vinod Kumar Yadav","doi":"10.1109/TDMR.2025.3646490","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3646490","url":null,"abstract":"Mismatch among solar cells induces a thermal imbalance between shaded and unshaded cell(s), ultimately causing premature failure of the PV module. Bypass diodes (BPD) have conventionally been used to resolve this issue; however, this study demonstrates the incompetence of BPD in mitigating hotspots when the shaded PV module is in array interconnect. In this study, three different <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> array topologies—Series-Parallel (SP), Bridge Linked (BL), and Total-Cross-Tied (TCT) are experimentally analyzed to assess BPD behavior. Results reveal that BPD fails to conduct across all interconnection topology, leading to hotspot formation, corroborated via thermographic pictures. notably, although a TCT-linked PV array exhibits minimal mismatch loss under partial shading, it suffers the highest misled loss and inferior thermal performance compared to other topologies. To address these challenges, this paper presents an improved hotspot detection and protection circuit (IHDPC), that enhances both electrical and thermal response of the PV systems by improving the sensitivity of BPD conduction towards shading. The efficacy of IHDPC is compared with the conventional BPD. Results indicate a substantial reduction in misled loss and maximum temperature of shaded module by up to 60.48% and 35.07%, respectively. Furthermore, IHDPC improves power generation, previously obstructed by hotspot protection circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"31-41"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation of the Single-Event Burnout in Lateral Enhancement-Mode β-Ga2O3 MOSFET Devices","authors":"Zefeng Wang;Fengkai Liu;Zhongli Liu;Xiangjie Cao;Xinrui Xu;Chengmin Bai;Jianqun Yang;Xingji Li","doi":"10.1109/TDMR.2026.3658196","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3658196","url":null,"abstract":"This study investigates the single-event burnout (SEB) mechanisms and hardening strategies of beta-gallium oxide (<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula>O<inline-formula> <tex-math>${}_{mathbf {3}}$ </tex-math></inline-formula>) enhancement-mode (E-mode) metal-oxide-semiconductor field-effect transistor (MOSFET) through technology computer-aided design (TCAD) simulations. Firstly, the accuracy of the simulation results was verified against relevant literature, and the necessity of including the substrate structure in the SEB simulation was demonstrated. Subsequently, transient analysis reveals a four-stage SEB evolution: (a) The large number of electron-hole pairs (EHPs) generated by heavy-ion incidence drift under the influence of the external field is collected by the electrodes. (b) Under the influence of the high electric field at the gate edge and the transient current induced by heavy ions, impact ionization is triggered, generating new EHPs. (c) The uniformly distributed hole pillars and the auxiliary gate depleted the channel, leading to transient current decay. (d) Substrate holes leave the region beneath the gate and are reduced through recombination, while channel holes accumulate at the gate interface, elevating the gate potential and maintaining the conductive channel until thermal burnout occurs. The thermal burnout in the final stage has been identified as the core process of its SEB. Based on this, we propose a source-connected Schottky body contact (SC-SBC) structure to extract excess holes under the gate in order to verify the SEB mechanism and attempt device hardening design. Simulation results demonstrate that this method effectively drains accumulated gate-region holes, suppresses gate potential elevation, and prevents SEB. The results also verified that the rise in gate potential due to hole accumulation beneath the gate is the fundamental mechanism responsible for SEB in lateral E-mode <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga<inline-formula> <tex-math>${}_{mathbf {2}}$ </tex-math></inline-formula>O<inline-formula> <tex-math>${}_{mathbf {3}}$ </tex-math></inline-formula> MOSFETs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"351-357"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148513217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation Behaviors Comparation and Analysis of Two Typical Trench SiC MOSFETs Under High Gate Voltage Stress","authors":"Peng Liao;Yanghao Wang;Jian-Bin Guo;Qing Qing Sun;David Wei Zhang;Hang Xu","doi":"10.1109/TDMR.2025.3649972","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3649972","url":null,"abstract":"This study investigates the degradation behaviors of two commercially available trench SiC MOSFETs with asymmetric trench gate and double trench gate under high gate voltage stress (both positive and negative). Experimental results reveal that the two gate structures exhibit markedly different degradation behaviors and temperature-dependent degradation responses after high gate voltage stress. Under high gate voltage stress, the double trench structure exhibits degradation behaviors analogous to conventional PBTI/NBTI phenomena, with enhanced degradation rates under negative gate voltage stress and temperature acceleration. In contrast, the asymmetric trench structure shows better reliability under equivalent stress conditions, particularly demonstrating negligible threshold voltage shift under negative bias. Temperature-dependent analysis revealed hole trapping at oxide layer dominates the asymmetric trench degradation process under positive bias, with anomalous threshold voltage reduction observed at high temperatures. Based on these findings, possible degradation mechanisms have been discussed and validated through C-V measurement. This work provides the detailed comparison of degradation behaviors between different gate structures under high gate voltage stress, offering valuable insights into the relationship between structural design and degradation mechanisms, which are critical for high-stress operational applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"292-300"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2026.3672946","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3672946","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11447435","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147557706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Radiation Degradation in CIS on Star Sensor’s Detection and Positioning Capabilities","authors":"Kunfang Li;Jie Feng;Lin Wen;Wei Zhang;Qi Guo;Yudong Li","doi":"10.1109/TDMR.2026.3665042","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3665042","url":null,"abstract":"Star sensors, high-precision instruments for spatial attitude determination, rely critically on the CMOS image sensor (CIS) for imaging. The performance of CIS degrades under space radiation, yet its impact on system-level performance remains insufficiently understood. This study conducted proton irradiation experiments (30 MeV) on CIS to analyze the degradation mechanisms of dark current, dark current non-uniformity, and quantum efficiency. Integrated into a star sensor system, the irradiated CIS showed degraded signal-to-noise ratio (SNR) under simulated star imaging. The effect of radiation-induced hot pixels on centroid positioning accuracy was also investigated, revealing that their impact depends on relative intensity and spatial distribution. This work provides a preliminary analysis of how device-level radiation effects translate to system-level performance degradation in star sensors.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"3-8"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148508514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Package-Level Electro-Thermal Simulation With Transient Thermal Resistance Model for Surge Stress Failure Analysis of SiC MOSFET","authors":"Zaiman Xiang;Tao Luo;Wenbo Wang;Bo Sun;Botao Sun;Qingchun Zhang;Guoqi Zhang;Jiajie Fan","doi":"10.1109/TDMR.2026.3655032","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3655032","url":null,"abstract":"This paper investigates the surge reliability of commercial 1200V SiC MOSFETs through a combined approach of experimental testing and multiphysics simulation, elucidating the failure mechanisms under both step and repetitive surge current stress. The innovative integration of package-level electro-thermal coupling simulation with transient junction temperature estimation overcomes the limitations of conventional methodologies that rely solely on decapsulation analysis and Technology Computer Aided Design (TCAD) simulation. Experimental evaluations on six Devices Under Test (DUTs) with distinct structural configurations, employing surge testing and failure analysis techniques including C-mode Scanning Acoustic Microscopy (C-SAM), optical microscopy, and Scanning Electron Microscope (SEM), confirm that device failure primarily originates from gate-source short circuits caused by aluminum bonding wire melting. COMSOL multiphysics simulations further replicate the transient thermal characteristics of bonding wire regions, demonstrating rapid temperature escalation to the Aluminum melting point within 5-6 ms during surge events. A transient thermal resistance-based junction temperature characterization method is proposed, revealing an inverse proportionality between thermal resistance and chip area.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 1","pages":"42-53"},"PeriodicalIF":2.7,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148509739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}