IEEE Transactions on Device and Materials Reliability最新文献

{"title":"An Improved Backpropagation Neural Network Method for Characterizing Performance Degradation of LDMOS Device Under Transmission Line Pulse Interference","authors":"Dongyan Zhao;Zheng-Wei Du;Qichao Wang;Kai-Yi Yang;Hao Xie;Fang Liu;Yaxing Zhu;Yingzong Liang;Wen-Yan Yin","doi":"10.1109/TDMR.2025.3614256","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3614256","url":null,"abstract":"With the wide applications of Lateral Diffused Metal-Oxide-Semiconductor (LDMOS) transistors in power conversion systems, their reliability has become a growing concern. It is also well known that electrostatic discharge (ESD) has long been the primary sources of electromagnetic interference, and its cumulative effects can result in the performance degradation of devices significantly. However, existing research on the characterization of performance degradation of LDMOS devices are mainly focused on their physical models, and accurately quantifying the degradation under diverse conditions still remain a challenge. Here, transmission line pulse (TLP) is used to simulate the ESD interference in LDMOS devices. One performance degradation prediction method, based on a multi-head incremental, i.e., improved backpropagation (BP) neural network (IBP-NN), is developed, where the input parameters as well as network structure are optimized, and therefore, the prediction accuracy of device degradation is enhanced greatly. Further, the degradation mechanisms of MOS devices are analyzed, followed by the validation of independence of different parameters affecting the degradation process. In particular, our experimental results show that the proposed method can perform well in predicting the safety or reliability of LDMOS devices under different electromagnetic pulse loading cases.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"934-943"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Insights Into the Effects of Interface Trap Charges on Electrostatic-Based Magnesium Silicide Tunneling Interface","authors":"Bandi Venkata Chandan;Kaushal Kumar Nigam","doi":"10.1109/TDMR.2025.3621826","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3621826","url":null,"abstract":"This work presents an in-depth analysis of a newly proposed electrostatically doped magnesium silicide Tunnel FET (ES-Mg2Si-TFET), developed to overcome key limitations in traditional TFET architectures. Conventional designs suffer from inadequate ON-state current <inline-formula> <tex-math>$(I_{mathrm {ON}})$ </tex-math></inline-formula> and sensitivity to random dopant fluctuations, both of which hinder their viability in ultra-low power electronics. To address these constraints, the ES-Mg2Si-TFET leverages a dual strategy involving dielectric modulation and source region optimization. Numerical simulations reveal a substantial enhancement in device performance, with <inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula> increased by nearly five orders of magnitude and subthreshold swing (SS) improved by 89% relative to conventional counterparts. Furthermore, the influence of interface trap charges (ITCs) on device stability is thoroughly investigated. Results show that the ES-Mg2Si-TFET maintains better immunity to ITC-induced flat-band voltage shifts compared to standard electrostatically doped TFETs. These advancements in both static and analog/RF figures of merit under low-voltage conditions establish the ES-Mg2Si-TFET as a strong contender for future energy-efficient integrated systems.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"921-933"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Electrical Breakdown in AlGaN/GaN/AlN HEMTs Through Nanoscale Analysis and Physics-Based Modeling","authors":"Björn Hult;Alok Ranjan;Lunjie Zeng;Eva Olsson;Niklas Rorsman;Andrei Vorobiev","doi":"10.1109/TDMR.2025.3621211","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3621211","url":null,"abstract":"The high-voltage operation of GaN power high-electron mobility transistors (HEMTs) is primarily limited by electric field crowding near the gate field plates, which, over time, can degrade the dielectric properties of the passivation layer or gate insulators and compromise device reliability. Therefore, understanding the different breakdown mechanisms—their causes and locations—is essential for optimizing device design and improving off-state performance. Previous studies have primarily focused on device reliability in GaN HEMTs with doped buffer layers. By contrast, this study focuses on the effects of prolonged off-state stress in Metal-Insulator-Semiconductor (MIS)-gated GaN HEMT with an AlGaN/GaN/AlN heterostructure design without a buffer layer. The devices are investigated using electrical characterization, nanoscale structural/chemical analysis (SEM, TEM, EDS). Additionally, technology computer-aided design (TCAD) simulations are employed to describe the breakdown process by studying the electric field and charge distribution in the dielectrics. Based on the structural/chemical analysis, as well as the TCAD simulation results, it is suggested that the formation of a vertical percolation path in the <inline-formula> <tex-math>$mathrm { SiN_{x}}$ </tex-math></inline-formula> passivation layer underneath the field plate edge initiates the destructive breakdown process.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"861-868"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Efficient Modeling Approach for Electrothermal Migration Analysis of On-Chip Interconnects","authors":"Da-Wei Wang;Wei Luo;Sen-Sen Li;Lin-Yuan Chen;Cheng-Hao Yu;Wen-Sheng Zhao","doi":"10.1109/TDMR.2025.3609820","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3609820","url":null,"abstract":"As technology nodes continue to shrink and advanced packaging technologies develop, the high temperature and electric field strength in integrated microsystems will further aggravate migration failures of chip interconnects. In this work, an efficient equivalent modeling approach for fast transient stress evolution estimation is proposed to implement the electrothermal migration effect investigation in specific of complex on-chip interconnects composed of linear interconnect segments. The physical model for electrothermal coupling migration effect is elaborated first, and then its equivalent modeling approach is proposed and explained with reference to transmission line theory. After that, the performance of proposed modeling method is studied through several cases, in which the accuracy and efficiency of established models are verified through comparing with numerical models. To further improve the computational efficiency of the equivalent models, especially for complex interconnects, an improved model order reduction method is implemented, and speedups of more than a dozen can be achieved.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"850-860"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Analysis of MOS Devices Using Burst Pulse CV Measurement Technique","authors":"Himanshu Marothya;Atul Sachan;Vishwas Acharya;Sandip Mondal","doi":"10.1109/TDMR.2025.3599336","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3599336","url":null,"abstract":"Reliability characterization of metal-oxide-semiconductor (MOS) devices requires fast capacitance–voltage (CV) measurement techniques to capture the effect of defect states before they recover. Bias Temperature Instability (BTI) is one such reliability issue where oxide traps accumulate under stress and relax when bias is removed. Conventional CV measurements require longer time to sweep the voltage that alters the defect states during the measurement. Here we demonstrate a Burst CV (BCV) measurement system capable of measuring the entire CV curve in less than <inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>s with a data sampling rate of 0.32 ns. The system offers burst pulse voltage range of ± 10 V, without disturbing the state of the device. The BCV system has been used to measure the BTI characteristics of an Aluminium Oxide Phosphate (ALPO) based two-terminal metal oxide semiconductor capacitor (MOScap) device by applying stress voltages from –10 V to –18 V for various durations (20 ms to 10 s) and measuring the shift of flatband voltage (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>VFB). The BTI characteristics of the devices reveals a sublinear power-law dependency (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>V<inline-formula> <tex-math>${_{text {FB}}}~propto $ </tex-math></inline-formula> tm) with exponents around 0.24–0.31, indicating trap generation rates. These findings confirm the advantage of BCV techniques for capturing fast trap dynamics and underscore the reliability potential of oxide-based devices under various stress conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"765-769"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148485503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of Electromagnetic Susceptibility in Optocouplers Exposed to Different Interference Waveforms","authors":"Peng Huang;Bing Li;Jiayue Xing;Donglin Su","doi":"10.1109/TDMR.2025.3608288","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3608288","url":null,"abstract":"An optocoupler is a widely used electrical control switching device that falls under the direct-current (DC) on/off category from a functional perspective. The datasheet for optocouplers typically provides DC characteristics and the delay time associated with the on/off switching transition. However, it often lacks detailed information regarding the device’s electromagnetic behavior and performance at radio frequencies (RF). To characterize the electromagnetic susceptibility (EMS) of optocouplers, we propose a new method that injects interference signals with different waveforms through direct power injection (DPI). This paper focuses on the EMS of two specific optocouplers, P521GB and PC817, which exhibit significant susceptibility to electromagnetic interference. The experimental results show that when the interference signal intensity exceeds the susceptibility threshold of the optocoupler, its operational state is altered, and the output voltage drops to a low level. Additionally, we present the susceptibility thresholds of the optocouplers under varying interference conditions. This study provides valuable insights into the electromagnetic susceptibility characteristics of optocouplers and offers data and theoretical support for the electromagnetic protection design of electronically controlled switching systems composed of optocouplers, which is of significant value.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"781-787"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148486930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Error-Corrected RRAM-Based Compute-in-Memory Accelerator Using Voltage-Clamp Current Mirror","authors":"Yu Liu;Wenqiang Zhang;Xiaofeng Song;Jianxing Zhou;Jingzheng Li;Haoran Feng;Wenjuan Lu;Chunyu Peng;Qiang Zhao;Chenghu Dai;Licai Hao;Xiulong Wu;Zhiting Lin","doi":"10.1109/TDMR.2025.3612983","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3612983","url":null,"abstract":"Computational reliability is a promising research direction in computing-in-memory (CIM), particularly in non-volatile memory (NVM) technologies such as resistive random-access memory (RRAM). Due to its outstanding performance and developmental potential, RRAM plays a critical role in advancing CIM research. The high computational reliability, low-cost ADC and low power consumption are the challenges for RRAM CIM. This study proposes an Error-corrected RRAM-based CIM architecture. To solve the problem of excessive calculation current, a voltage clamp current mirror (VCCM) is designed to improve the calculation accuracy and control calculation power consumption. A new quantization method is proposed to avoid the introduction of complex quantization circuits and reduce the energy consumption of quantization. To address the issue of significant errors in small RRAM HRS/LRS, a new error-correction quantization function is proposed. This function better aligns with the computational characteristics of the CIM macro, thereby improving robustness. The macro design is evaluated under TSMC 28-nm technology node. At <inline-formula> <tex-math>$V_{ref}$ </tex-math></inline-formula> of 100 mV, the proposed macro can run at 120.5 MHz. The energy efficiency for the CIM macro reaches 78.62 TOPS/W under the condition of 4-bit input and 4-bit output. The calculation accuracy on the MNIST and CIFAR-10 dataset are 99.6% and 91.2%, even with a significant process disturbance and memristor resistance fluctuation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"788-801"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148486926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wide-Range Threshold Voltage Control of Dual-Inner-Gate Gate-All-Around Field-Effect Transistor","authors":"Seungjoon Jeong;Changhwan Shin","doi":"10.1109/TDMR.2025.3605684","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3605684","url":null,"abstract":"Gate-all-around field-effect transistors (GAAFETs) have been known to outperform FinFETs. However, their complex structure poses several process-induced challenges, primarily associated with implementing multiple threshold voltage (Vth) options within a limited voltage range. The “dipole-layer” and “inner-outer” gate technique have been developed to secure various <inline-formula> <tex-math>$mathrm {V}_{th}$ </tex-math></inline-formula> values for a given voltage range. However, these approaches show high <inline-formula> <tex-math>$mathrm {V}_{th}$ </tex-math></inline-formula> variability or lower on-state drive current (Ion). In this work, we introduce two types of inner gates to secure more diverse <inline-formula> <tex-math>$mathrm {V}_{th}$ </tex-math></inline-formula> values over a wide range while minimizing the degradation of on-state drive current. We have developed an inner–outer gate process compatible with conventional GAAFET and identified and optimized DC and AC performance-affecting parameters. This study demonstrates that dual-inner gate (DIG)-GAAFETs are compatible with the conventional GAAFET process, offering five <inline-formula> <tex-math>$mathrm {V}_{th}$ </tex-math></inline-formula> levels, up to 11.7% shorter RC delay, up to 25.6% higher Ion, and lower <inline-formula> <tex-math>$mathrm {V}_{th}$ </tex-math></inline-formula> variability. These improvements address the issue of limited <inline-formula> <tex-math>$mathrm {V}_{th}$ </tex-math></inline-formula> levels, facilitating versatile applications of GAAFET structures in industry.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"878-886"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Location-Aware Error Correction for Mitigating the Impact of Interconnects on STT-MRAM Reliability","authors":"Surendra Hemaram;Tommaso Marinelli;Mahta Mayahinia;Mehdi B. Tahoori;Francky Catthoor;Siddharth Rao;Fernando Garcia Redondo;Gouri Sankar Kar","doi":"10.1109/TDMR.2025.3627442","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3627442","url":null,"abstract":"Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing memory technologies. However, STT-MRAM faces reliability challenges, primarily due to stochastic switching characteristics, process variation, and manufacturing defects. Furthermore, these reliability challenges worsen as technology scales down due to the increasing dominance of interconnect parasitic resistive-capacitive (RC) effects. We propose an efficient location-aware error-correcting code (ECC)-based strategy for mitigating the impact of interconnect parasitics on STT-MRAM bit-cell reliability. By applying a non-uniform error correction mechanism across different memory zones, our approach increases correction strength with distance from the driver. The proposed approach avoids the need for uniformly strong error correction across the whole memory zone, thereby reducing ECC parity bit memory overhead while improving the reliability in the vulnerable memory zone. Furthermore, the proposed strategy has a negligible effect on system performance, as measured by instructions per cycle (IPC).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"828-842"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148484362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin","authors":"Lomash Chandra Acharya;Neha Gupta;Khoirom Johnson Singh;Mahipal Dargupally;Neeraj Mishra;Arvind Kumar Sharma;Ajoy Mandal;Venkatraman Ramakrishnan;Sudeb Dasgupta;Anand Bulusu","doi":"10.1109/TDMR.2025.3603098","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3603098","url":null,"abstract":"This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage <inline-formula> <tex-math>$(V_{mathrm {th}})$ </tex-math></inline-formula> denoted by <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of <inline-formula> <tex-math>$Delta V_{mathrm {th}}$ </tex-math></inline-formula> is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28 nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately ~99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 4","pages":"810-819"},"PeriodicalIF":2.7,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148486928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}