IEEE Transactions on Device and Materials Reliability最新文献

{"title":"Unit-Cell-Based Approach for Electromigration Compliance Checks in VLSI Power Delivery Networks","authors":"Simone Esposto;Ivan Ciofi;Giuliano Sisto;Kristof Croes;Dragomir Milojevic;Houman Zahedmanesh","doi":"10.1109/TDMR.2025.3566054","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3566054","url":null,"abstract":"As the electromigration (EM) reliability margin reduces rapidly with scaling, novel approaches for EM-compliance checks are being intensively sought to enable more accurate and less conservative analyses. Currently, chip-level EM reliability is assessed based on the failure probability of individual lines and vias in the BEOL stack, overlooking potential redundant connections that could still ensure circuit operation despite isolated failures. This is particularly relevant for the power delivery network (PDN), which is redundant by definition due to its regular mesh structure. In this work, we leverage a new approach to perform EM-compliance checks that relies on considering the PDN as a matrix of identical network units-cells, henceforth referred to as tiles, and using them to compute the overall failure risk. As opposed to conventional methods, our approach captures the impact of redundancy within each individual PDN tile, thereby providing less conservative reliability estimations. After reviewing standard methods for EM-compliance checks, namely limit-based and statistical EM budgeting (SEB), we quantify the additional reliability margin provided by our PDN-tile approach. For our analysis, we considered a PDN featuring three different metallization schemes for Dual Damascene (DD) Cu/Low-k interconnects utilizing SiCN capping, Cobalt (Co) capping with and without Ruthenium (Ru) via prefill. Using the standard SEB method indicated that Co capping and Co capping + Ru Via Prefill lead to reductions in EM failure risk by 5 and 7 orders of magnitude, respectively, compared to SiCN capping. The new approach was implemented for the first metallization with SiCN capping. At 10 years lifetime, our PDN-tile approach foresees a failure probability which is 3 orders of magnitude smaller than the SEB approach. At an equivalent failure probability of 100ppm and the same target lifetime of 10 years, the current of standard cells can be increased by 2.8-fold, giving designers more margin to improve chip performances.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"232-239"},"PeriodicalIF":2.5,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FPGA Assessment Methodology of Adverse X-Ray Effects on Secure Digital Circuits","authors":"Nasr-Eddine Ouldei Tebina;Luc Salvo;Nacer-Eddine Zergainoh;Guillaume Hubert;Paolo Maistri","doi":"10.1109/TDMR.2025.3538484","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3538484","url":null,"abstract":"Recent research demonstrates the feasibility of X-ray attacks. Unlike traditional fault injection methods, X-rays offer precise spatial targeting because of their short wavelength and high penetration power. This allows attackers to selectively target specific regions within a device, from individual transistors to larger blocks. This necessitates a new perspective on hardening techniques, requiring designers to consider the impact of X-ray irradiation on both fault injection and power consumption. To address this challenge, the paper proposes a characterization flow that analyzes the differences in side-channel leakages of FPGA components and their susceptibility to increased leakage due to X-ray effects. Despite the fundamental differences between ASIC and FPGA layouts, they both share the characteristic of being MOS technology-based, which makes them both susceptible to TID effects. The simulation results strongly support the theory that X-rays can induce leakage currents, thereby amplifying the side-channel information leakage observed in our experiments on FPGAs. Furthermore, these results provide concrete evidence that different FPGA components exhibit varying susceptibility to X-ray-induced leakage. Our findings reveal a clear hierarchy of vulnerability, with interconnects being the most susceptible elements, followed by registers, and lastly, logic components (LUTs and MUXes). This differential vulnerability offers valuable information for designers of secure cryptographic circuits. By understanding how X-rays impact different components, hardening techniques can be strategically targeted to provide the most effective protection against both fault injection and side-channel leakage.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"85-94"},"PeriodicalIF":2.5,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Equivalent Circuit Model of 12 nm P-FinFET for NBTI Effect","authors":"Jun-An Zhang;Hao Chen;Bo Liu;Chao Li;Dan Li;Tiehu Li;Yunhua Lu;Qingwei Zhang","doi":"10.1109/TDMR.2025.3543863","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3543863","url":null,"abstract":"A negative bias temperature instability (NBTI) equivalent circuit model based on P-FinFET of a 12nm CMOS PDK and electrical components and arithmetic units of EDA software is presented. The P-FinFET circuit model consists of electrical components such as voltage sources, controlled sources, adders and multipliers, and other arithmetic units. The model is set up with five tunable input parameters, including stress time, gate width, gate length, process corner (slow/ fast/ typical), and temperature. The equivalent circuit model also takes into account bias conditions of transistor, such as gate-source voltage, drain source voltage, and drain gate voltage, which will affect NBTI. Simulation result shows that the degradation curves of the equivalent circuit model for P-FinFET are in concordance with experimental data presented in previously published literatures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"247-252"},"PeriodicalIF":2.5,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructural Evolution of Gate Oxide in SiC Power MOSFETs Under Heavy-Ion Irradiation","authors":"Yiping Xiao;Chaoming Liu;Jiaming Zhou;Mingzheng Wang;Chunhua Qi;Tianqi Wang;Mingxue Huo","doi":"10.1109/TDMR.2025.3544208","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3544208","url":null,"abstract":"Maintaining the robustness of the gate oxide is a prerequisite for the on-orbit application of SiC MOSFETs. Recent research has demonstrated that the oxide undergoes premature breakdown within the operating voltage range after heavy ion irradiation, which is attributed to the activation of ion-induced gate latent damages (LDs) under gate post-irradiation gate stress (PIGS). However, the specific activation processes of LDs and oxide failure mechanism are not well understood. This study indicates that the dielectric breakdown induced epitaxy (DBIE) and thermal runaway effects are the dominant mechanisms when oxide rupture occurs, characterized by a step-like increase in gate leakage current during PIGS test. The failure analysis further confirmed the formation of DBIE hillock and percolation path. The results suggest that more attention should be paid to the gate oxide reliability before SiC MOSFETs could replace their Si-based counterparts in aerospace applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"189-194"},"PeriodicalIF":2.5,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"From Ground to Orbit: A Robust and Efficient Test Methodology for RISC-V Soft-Cores","authors":"Bruno Forlin;Kevin Böhmer;Carlo Cazzaniga;Paolo Rech;Gianluca Furano;Nikolaos Alachiotis;Marco Ottavi","doi":"10.1109/TDMR.2025.3537718","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3537718","url":null,"abstract":"As traditional space-grade computing systems struggle to meet the increasing computational demands of modern space missions, RISC-V emerges as a promising alternative due to its open-source and highly customizable nature. However, the extensive hardware customization options in RISC-V introduce complexity in validation, making it challenging to ensure system reliability. This paper introduces a robust methodology for validating RISC-V-based systems under accelerated radiation beams, focusing on test uptime, leveraging Commercial Off-The-Shelf (COTS) FPGA devices, which offer flexibility and cost-effectiveness, to enable concurrent hardware and software development. We demonstrate how our methodology offers a comprehensive approach for testing heterogeneous systems on FPGAs, balancing thorough integration with cost-efficiency and test robustness. During our experiments with accelerated neutrons to assess the resilience of RISC-V cores, our approach guaranteed the correct delivery of 100% of the packages, while minimizing system downtime during radiation testing by reducing the Test Fixture SEFI cross-section.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"27-36"},"PeriodicalIF":2.5,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges","authors":"Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma","doi":"10.1109/TDMR.2025.3533004","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3533004","url":null,"abstract":"The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I<inline-formula> <tex-math>$_{text {ON}}$ </tex-math></inline-formula>) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V<inline-formula> <tex-math>$_{text {DS}} = 0.3$ </tex-math></inline-formula>V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"163-172"},"PeriodicalIF":2.5,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2024 Index IEEE Transactions on Device and Materials Reliability Vol. 24","authors":"","doi":"10.1109/TDMR.2025.3528093","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3528093","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"665-682"},"PeriodicalIF":2.5,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10841807","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142975942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive TCAD-Based Single Event Effect Study of TFET-Based 1T DRAM and Crossbar Memory Array","authors":"Dhananjay Prakash;Neha Kamal;Avinash Lahgere","doi":"10.1109/TDMR.2025.3528903","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3528903","url":null,"abstract":"In this paper, a comprehensive TCAD-based single event effect (SEE) study on tunnel field effect transistor (TFET) based one transistor dynamic random access memory (1T DRAM) and crossbar memory array is demonstrated through well-calibrated 2-D TCAD simulations. The simulation study reveals that the regions near Gate 2 are more susceptible to SEE. In addition, in comparison to without SEE, when a high energy particle (HEP) strikes the device, the read “1” (R1) current remains the same, however, the read “0” (R0) current increases <inline-formula> <tex-math>$sim ~10times $ </tex-math></inline-formula> at 358 K. As a result, the read current ratio (IR1/I<inline-formula> <tex-math>$_{mathrm {R0}}$ </tex-math></inline-formula>) and the sense margin (SM) decreases. The IR1/IR0 ratio with SEE is found to be <inline-formula> <tex-math>$sim ~10^{2}$ </tex-math></inline-formula>, which is <inline-formula> <tex-math>$10times $ </tex-math></inline-formula> lower than ratio without SEE. In addition, the impact of various parameters such as linear energy transfer (LET), HEP strike time, HEP strike moment, and HEP radius on TFET-based 1T DRAM performance is also evaluated. Moreover, for a 2 x 2 crossbar memory array, the combination of SEE with word line disturbance mechanism causes <inline-formula> <tex-math>$sim ~10times $ </tex-math></inline-formula> reduction in the R1 current at 358 K. Our findings will pave the way for further exploration and designing radiation-hardened TFET-based 1T DRAM for future low-power space applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"156-162"},"PeriodicalIF":2.5,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cryogenic Total Ionizing Dose Effects and Annealing Behaviors of SiGe HBTs","authors":"Jianan Wei;Peijian Zhang;Xiaohui Yi;Min Hong;Xiaojun Fu;Xinyue Tang;Kun Qian;Xiaolei Zhang;Wenlong Liao;Jiandong Zang;Lei Zhang;Ting Luo;Yunchen Wu","doi":"10.1109/TDMR.2024.3523303","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3523303","url":null,"abstract":"The total ionizing dose (TID) responses of <inline-formula> <tex-math>$0.35~mu $ </tex-math></inline-formula>m and <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m SiGe HBTs at liquid-nitrogen temperature (78 K) were investigated using 10 keV X-rays. For the first time, we compared the annealing behaviors of SiGe HBTs irradiated at 78 K and room temperature (297 K). The results reconfirm that SiGe HBTs have superior TID tolerance up to Mrad(Si) levels, and the current gain degradation of DUTs irradiated at 78 K is much less than those irradiated at 297 K. However, the <inline-formula> <tex-math>$0.35~mu $ </tex-math></inline-formula>m SiGe HBTs irradiated at 78 K show further degradation after room temperature annealing (RTA) due to the thermal activation of oxide charge migration and the long-term buildup of interface traps. The <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m SiGe HBTs irradiated at 78 K show minor change after RTA, which can be attributed to the competition between interface trap creation and annealing.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"150-155"},"PeriodicalIF":2.5,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation Behavior and Mechanism of SONOS FLASH by Total Ionization Dose Effects","authors":"Y. D. Wei;G. Z. Liu;J. H. Wei;W. Zhao;Y. Q. Wei;Y. Zhou;Z. Y. Sui;M. J. Liu;H. Ju;Y. Gao;H. Yang;J. P. Sun;Y. Liu","doi":"10.1109/TDMR.2024.3524100","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3524100","url":null,"abstract":"In this paper, the 2T SONOS FLASH is designed and fabricated based on 180 nm embedded FLASH process which includes one MOSFET and one SONOS FLASH transistor. The FLASH transistors are programmed and erased by band-to-band tunneling-induced hot electron and Fowler-Nordheim to realize different levels, and the mechanisms of the electrical degradation caused by radiation are investigated by the mid-gap technique. In order to clarify the degradation mechanism from the physical level, the first principle calculations are performed from the atomic and electronic term. The electric fields and the external environment are proved to play a crucial role in the charge loss. The higher electric fields can exacerbate the formation of the oxide charge, and the anti-radiation hardness can be achieved with oxygen-rich environment. The external field can efficiently change the electronic properties of <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-SiO2 with oxygen vacancy and hydrogen. This study provides a novel perspective of electrical degradations on the SONOS FLASH unit in different levels from both the experiments and theoretical simulations, which can be helpful for the design of advanced computational chips in space.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"128-133"},"PeriodicalIF":2.5,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}