IEEE Transactions on Device and Materials Reliability最新文献_第9页

An Aging Monitoring Method of Bond Wires Based on Voltage Ringing Frequency Characteristics in IGBT Modules 基于 IGBT 模块电压振铃频率特性的键合丝老化监测方法

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-29 DOI: 10.1109/TDMR.2024.3394517

Xiyuan Huang;Mingxing Du;Hongze Fu;Sai Gao

引用次数: 0

Device Reliability and Effect of Temperature on Memristors: Nanostructured V₂O₅ 器件可靠性和温度对晶闸管的影响：纳米结构 V2O5

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-23 DOI: 10.1109/TDMR.2024.3392634

Sharmila B;Ashutosh Kumar Dikshit;Priyanka Dwivedi

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Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond 针对 130 纳米至 28 纳米节点及更高节点超大规模器件的离态 TDDB 下通用介质击穿建模

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-22 DOI: 10.1109/TDMR.2024.3387271

Tidjani Garba-Seybou;Alain Bravaix;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho

{"title":"Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond","authors":"Tidjani Garba-Seybou;Alain Bravaix;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho","doi":"10.1109/TDMR.2024.3387271","DOIUrl":"10.1109/TDMR.2024.3387271","url":null,"abstract":"This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000 value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"174-183"},"PeriodicalIF":2.5,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140635661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Modeling of Temperature Rises at Focal-Plane-Array and Their Impact on the Performance of a CCD-Based Spaceborne Earth-Observing Imaging System 焦平面阵列温度上升模型及其对基于 CCD 的空间地球观测成像系统性能的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-18 DOI: 10.1109/TDMR.2024.3390798

Chahira Serief;Nassima Khorchef;Youcef Ghelamallah

{"title":"Modeling of Temperature Rises at Focal-Plane-Array and Their Impact on the Performance of a CCD-Based Spaceborne Earth-Observing Imaging System","authors":"Chahira Serief;Nassima Khorchef;Youcef Ghelamallah","doi":"10.1109/TDMR.2024.3390798","DOIUrl":"10.1109/TDMR.2024.3390798","url":null,"abstract":"Space optical imaging systems are subject during their in-orbit lifetime to many damaging effects caused by aging and harsh conditions (temperature and radiation) in the low Earth orbit environment threatening consequently instruments’ performance and durability. In particular, the time-dependent increase of the detector’s thermally-induced dark current due to temperature rises at the Focal-Plane-Array (FPA) may well lead to an unacceptable degradation in the radiometric performance of the optical imager. The aim of this work is to establish measures for the mitigation of FPA thermal effects on the radiometric performance and calibration of a space-borne optical imaging payload through FPA design optimization and in-orbit operation of the optical imaging payload. The temperature rises at FPA during long strip acquisition are first modeled, and results are used to assess the consequent effect on radiometric performance by predicting time-variable changes in detector offset due to thermal leakage current. Then, based on the outcomes of the thermal model and offset signals calculation, recommendations regarding FPA design and the operation of the optical imaging payload are made to mitigate the effect of FPA temperature rises on the imager’s radiometric performance. Finally, in-flight FPA temperature measurements taken during on-orbit operation are compared with the FPA thermal model results. The modeling results exhibit a strong correspondence with the measurements acquired during the flight. The dark current derived from in-flight data demonstrates that the time-dependent increase in the detector offset signals induced by temperature rises at FPA during image acquisition is negligible, validating the proposed thermal mitigation strategy.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"335-343"},"PeriodicalIF":2.5,"publicationDate":"2024-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140624935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width 具有不同 JFET 宽度的六角形平面 SiC VDMOSFET 的特性和 UIS 研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-16 DOI: 10.1109/TDMR.2024.3388482

Hou-Cai Luo;Huan Wu;Jing-Ping Zhang;Bo-Feng Zheng;Lei Lang;Guo-Qi Zhang;Xian-Ping Chen

{"title":"Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width","authors":"Hou-Cai Luo;Huan Wu;Jing-Ping Zhang;Bo-Feng Zheng;Lei Lang;Guo-Qi Zhang;Xian-Ping Chen","doi":"10.1109/TDMR.2024.3388482","DOIUrl":"10.1109/TDMR.2024.3388482","url":null,"abstract":"The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L\u0000<inline-formula> <tex-math>${_{text {JFET}}} = 1.4mu $ </tex-math></inline-formula>\u0000m has the best HF-FOM (R\u0000<inline-formula> <tex-math>${_{text {on}}} times $ </tex-math></inline-formula>\u0000Cgd) and HF-FOM (R\u0000<inline-formula> <tex-math>${_{text {on}}} times $ </tex-math></inline-formula>\u0000Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"323-328"},"PeriodicalIF":2.5,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140608373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Aging Reliability Compact Modeling of Trap Effects in Power GaN HEMTs 功率 GaN HEMT 中陷阱效应的老化可靠性紧凑建模

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-12 DOI: 10.1109/TDMR.2024.3387573

Yanfeng Ma;Sheng Li;Mengli Liu;Weihao Lu;Mingfei Li;Siyang Liu;Long Zhang;Jiaxing Wei;Lanlan Yang;Weifeng Sun;Jiaxin Sun

{"title":"Aging Reliability Compact Modeling of Trap Effects in Power GaN HEMTs","authors":"Yanfeng Ma;Sheng Li;Mengli Liu;Weihao Lu;Mingfei Li;Siyang Liu;Long Zhang;Jiaxing Wei;Lanlan Yang;Weifeng Sun;Jiaxin Sun","doi":"10.1109/TDMR.2024.3387573","DOIUrl":"10.1109/TDMR.2024.3387573","url":null,"abstract":"This article proposes an aging reliability compact model with high accuracy to simulate trap effects after long-term aging in power Gallium Nitride (GaN) based high electron mobility transistors (HEMTs). Dynamic on-state resistance \u0000<inline-formula> <tex-math>$(R_{mathrm{ on,dy}})$ </tex-math></inline-formula>\u0000 caused by trap effects is taken as an example to deliver the aging reliability modeling concepts and flows. Based on the mechanism of trap effects and accelerated-stress experiments, the variation model of electron mobility has been established, so that the degradation of \u0000<inline-formula> <tex-math>$R_{mathrm{ on,dy}}$ </tex-math></inline-formula>\u0000 after aging can be predicted. The structure of the advanced SPICE model for GaN HEMT (ASM-HEMT) is modified to integrate the mobility variation model into SPICE for convenient usage. In addition, the accuracy of the proposed model has been verified, and the RMSE value between measured data and simulated data under long-term high temperature reverse bias stress conditions is only 1.68%, thus the hazard of the power system caused by traps can be discovered and avoided in advance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"313-322"},"PeriodicalIF":2.5,"publicationDate":"2024-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TDDB Lifetime Reduction From Charging Damage in a 3D Vertical NAND Memory Technology 三维垂直 NAND 存储器技术中因充电损伤而缩短的 TDDB 寿命

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-10 DOI: 10.1109/TDMR.2024.3387305

Daniel Beckmeier;Charles LaRow;Andreas Kerber

{"title":"TDDB Lifetime Reduction From Charging Damage in a 3D Vertical NAND Memory Technology","authors":"Daniel Beckmeier;Charles LaRow;Andreas Kerber","doi":"10.1109/TDMR.2024.3387305","DOIUrl":"10.1109/TDMR.2024.3387305","url":null,"abstract":"Plasma Induced Damage (PID) testing methodology is applied to a Vertical Floating-Gate 3D NAND Memory Technology with CMOS under Array (CuA) and detected lifetime effects are reported for the first time. Revealing Constant Current Stresses (CCS) at elevated temperature of 95°C are performed to identify process charging risks. The effect on transistor dielectric breakdown lifetimes from PID induced defects are quantified by a Constant Voltage Stress (CVS) test methodology and modeled by combining intrinsic and extrinsic failure distributions scaled by antenna size. To determine the voltage dependence of the early fails, a larger sample size is stressed at varying gate stress voltages. The tests show the same intrinsic power law voltage acceleration while for larger antennas the extrinsic branches increase with reduced gate stress voltage. The empirical bimodal TDDB model with added intrinsic/extrinsic power law terms for the gate stress voltage can describe the behavior with high accuracy. A physical model using the gate current voltage characteristics and the antenna area ratios as inputs is developed, which describes the behavior also with good agreement. Probing pad charging damage effects are further analyzed by TDDB tests on capacitor structures of varying gate dielectric areas for n- and pMOS devices of different dielectric thicknesses.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"203-210"},"PeriodicalIF":2.5,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors 基于堆叠晶体管的低面积、低延迟三节点跃迁自恢复设计

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-10 DOI: 10.1109/TDMR.2024.3386954

Hui Xu;Jiuqi Li;Ruijun Ma;Huaguo Liang;Chaoming Liu;Senling Wang;Xiaoqing Wen

{"title":"A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors","authors":"Hui Xu;Jiuqi Li;Ruijun Ma;Huaguo Liang;Chaoming Liu;Senling Wang;Xiaoqing Wen","doi":"10.1109/TDMR.2024.3386954","DOIUrl":"10.1109/TDMR.2024.3386954","url":null,"abstract":"With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"302-312"},"PeriodicalIF":2.5,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Characteristics and Reliability With Channel Length Dependent on the Deposited Sequence of SiO₂ and Si₃N₄ as PV in LTPS TFTs LTPS TFT 中取决于作为 PV 的 SiO2 和 Si3N4 沉积顺序的沟道长度的特性和可靠性

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-01 DOI: 10.1109/TDMR.2024.3379743

Chuan-Wei Kuo;Tsung-Ming Tsai;Ting-Chang Chang;Hong-Yi Tu;Yu-Hsiang Tsai;Jian-Jie Chen;I-Yu Huang

{"title":"The Characteristics and Reliability With Channel Length Dependent on the Deposited Sequence of SiO₂ and Si₃N₄ as PV in LTPS TFTs","authors":"Chuan-Wei Kuo;Tsung-Ming Tsai;Ting-Chang Chang;Hong-Yi Tu;Yu-Hsiang Tsai;Jian-Jie Chen;I-Yu Huang","doi":"10.1109/TDMR.2024.3379743","DOIUrl":"10.1109/TDMR.2024.3379743","url":null,"abstract":"This study investigates the characteristics on different channel lengths for a sequence of Si3N4 and SiO2 deposition as PV of LTPS TFTs. After analyzing the subthreshold swing (SS) of the initial condition and change in the \u0000<inline-formula> <tex-math>$Delta text{V}_{text{TH}}$ </tex-math></inline-formula>\u0000 after NBTI and PBTI operations, a degradation mechanism is identified. When Si3N4 is deposited as the first layer of passivation (PV), hydrogen diffuses into the channel owing to activation or thermal annealing. As the channel length decreases, the hydrogen concentration increases at the center of the channel for devices with Si3N4 as the first layer of PV. Elevated hydrogen concentrations in the center of short channel devices lead to a debased SS. Moreover, the more positive fixed oxide charges create a more pronounced degradation after NBTI operation. On the other hand, PBTI performance shows a milder degradation with decreasing channel length due to fewer trapping charges. Finally, the hydrogen concentration is verified using SIMS. In summary, the heightened degradation of NBTI with device scaling is attributed to excess hydrogen on channel center during Si3N4 film deposition. The uneven hydrogen distribution also contributes the different SS and the different degradation after PBTI operation with different channel length.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"268-274"},"PeriodicalIF":2.5,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

From Accelerated to Operating Conditions: How Trapped Charge Impacts on TDDB in SiO₂ and HfO₂ Stacks 从加速条件到工作条件：捕获电荷如何影响二氧化硅和二氧化铪叠层中的 TDDB

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-01 DOI: 10.1109/TDMR.2024.3384056

Sara Vecchi;Andrea Padovani;Paolo Pavan;Francesco Maria Puglisi

{"title":"From Accelerated to Operating Conditions: How Trapped Charge Impacts on TDDB in SiO₂ and HfO₂ Stacks","authors":"Sara Vecchi;Andrea Padovani;Paolo Pavan;Francesco Maria Puglisi","doi":"10.1109/TDMR.2024.3384056","DOIUrl":"10.1109/TDMR.2024.3384056","url":null,"abstract":"Despite the various well-established theories such as the thermochemical (E-model), \u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000 E-model, power law \u0000<inline-formula> <tex-math>$(V^{N}$ </tex-math></inline-formula>\u0000-model), and 1/E-model, accurately replicate dielectric breakdown (BD) experimental trends in accelerated conditions, they diverge significantly in lifetime estimations when projecting to operating conditions. The recently introduced Carrier Injection (CI) model successfully reconciles the discrepancies observed in the aforementioned theories within a unified framework, revealing that the time-dependent dielectric breakdown (TDDB) E-field dependence can change from thermochemical to power-law, and even to 1/E trend, depending on the microscopic properties of key atomic species (precursors). Notably, these findings were based on the assumption that the electric field in the dielectric is solely influenced by the applied bias, disregarding the impact of trapped charge at defects and precursors. Nevertheless, it is recognized that trapped charge significantly contributes to the local electric field within the oxide at low applied voltages, leading to a substantial difference between accelerated and operating conditions. With that in mind, this paper incorporates the influence of trapped charges into the CI model, offering a more complete explanation of the BD phenomenon in SiO2 and HfO2 stacks. The research demonstrates that, depending on the material system and the nature of defect precursors in the oxide, the presence of trapped charge can result in significant deviations from TDDB lifetime predictions derived from conventional models. Furthermore, the study explores the combined impact of trapped charge and the microscopic properties of defect precursor sites on TDDB and leakage current through the oxide.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"194-202"},"PeriodicalIF":2.5,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0