IEEE Transactions on Device and Materials Reliability最新文献

{"title":"Detection and Analysis of Stress Wave in MOSFET Under Gate-Source Overvoltage Failure","authors":"Guangxin Wang;Yunze He;Xuefeng Geng;Longhai Tang;Songyuan Liu;Qiying Li;Kai Zhang","doi":"10.1109/TDMR.2023.3345306","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3345306","url":null,"abstract":"As a real-time, online, and non-invasive monitoring method, acoustic emission (AE) monitoring technology has a promising future in the condition monitoring and fault diagnosis of power devices such as power MOSFETs. Stress waves are generated when power MOSFETs are turned on and off. Currently, most scholars have only researched the influence of circuit parameters on stress waves in normal devices or the relationship between stress waves and the aging state of devices or modules. However, the correlation between the characteristics of the stress wave and the specific failures inside the device has not been determined. As a result, the experiment for gate-source overvoltage failure was carried out in this work. The differential acoustic emission sensor was used to acquire stress waves of power MOSFETs under different gate-source voltages, including stress waves during chip overvoltage failure. The characteristics of stress waves are analyzed from the perspectives of time-domain and frequency-domain, and it can be concluded that the time-domain peak-to-peak value, signal energy, and wavelet peak value of the stress wave during the failure process are significantly different from those under normal conditions. The experimental results laid the groundwork for making a connection between device failures and the characteristics of the stress wave, which indicates that it will be possible to apply the acoustic emission monitoring technology to the fault diagnosis of power devices in the future.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"89-97"},"PeriodicalIF":2.0,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analyzing Total-Ionizing-Dose Induced Memory Window Degradation in Ferroelectric FinFET","authors":"Sola Woo;Khandker Akif Aabrar;Suman Datta;Shimeng Yu","doi":"10.1109/TDMR.2023.3344710","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3344710","url":null,"abstract":"The total-ionizing-dose (TID) effect of ferroelectric FinFET structure (Fe-FinFET) is analyzed under various gamma ray irradiation conditions. An TCAD model is developed to understand the physical mechanism of TID effect, and the simulation results are calibrated with the experimental data. We show that the TID-induced memory window degradation is attributed to two types of traps being generated within the ferroelectric layer and at the interfacial layer/silicon interface. Furthermore, the impact of the scaling down the Fe-FinFET structure is investigated with various gate lengths and fin widths. The projection shows that the scaled Fe-FinFET still could maintain a 0.4 V memory window under the highest radiation dose (10 Mrad). The sufficient memory window under the highest irradiation condition confirms the survivability of the Fe-FinFETs and makes Fe-FinFET a promising candidate for data storage as radiation-hard non-volatile memory in harsh ionizing environment.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"84-88"},"PeriodicalIF":2.0,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Utilizing Two Three-Transistor Structures for Designing Radiation Hardened Circuits","authors":"Xin Liu;Jiaxin Chen;Yinyu Liu;Ke Gu;Siqi Wang;Jianhui Bu;Quanfeng Zhou","doi":"10.1109/TDMR.2023.3344767","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3344767","url":null,"abstract":"This paper focuses on two types of three-transistor structures, known as PNN and PPN, which represent the number of PMOS and NMOS transistors in each configuration. These structures are characterized by their unidirectional flip at the output nodes, as they are spatially surrounded by N-type and P-type diffusion regions respectively. This characteristic makes them suitable for designing radiation-hardened circuits, particularly for Single Event Upset (SEU) tolerance. Three dimensional (3-D) simulations demonstrate that when exposed to energetic particles, the node surrounded by N-type diffusion remains immune to 0\u0000<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>\u00001 flips, while the node surrounded by P-type diffusion remains immune to 1\u0000<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>\u00000 flips. Additionally, the proposed three-transistor blocks ensure that a conducting path from the voltage supply to ground is never formed, thereby preventing excessive power consumption. Building upon these distinct structures, we propose two area-efficient Single-Node-Upset (SNU) tolerant latches, and two Double-Node-Upset (DNU) recoverable latches. Extensive simulations confirm that our proposed latches, referred to as SNUTL-PNN, SNUTL-PPN, DNURL-PNN and DNURL-PPN, exhibit outstanding self-recovery capability in terms of their output nodes. A comparison with other designs reveals that the latches presented in this paper demonstrate advantages in area and power consumption. Moreover, we applied a variant of PNN and PPN to the dynamic flip-flop, True Single Phase Clock (TSPC), which usually operates with little power and at high speeds. Our introduced hardened scheme occupies minimal area, possess short propagation delays, and exhibit relatively low power consumption under normal operating conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"68-76"},"PeriodicalIF":2.0,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability and Optimization Simulation Study of Zero-Temperature-Delay Point in Digital Circuits for Advanced Technology","authors":"Mingyue Zheng;Wangyong Chen;Yaoyang Lyu;Linlin Cai","doi":"10.1109/TDMR.2023.3344639","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3344639","url":null,"abstract":"Thermal challenges are increasingly significant for advanced technology, and the operating environment with large temperature variation also acts as one of the crucial threats to the system’s performance and reliability. To improve the temperature immunity of digital circuits, in this work, the supply voltage (VDD) making the delay immune to temperature variation is identified, which differs from the zero-temperature-coefficient (ZTC) point used in analog applications and is defined as the zero-temperature-delay (ZTD) point. The dependencies and optimal selection of ZTD point in digital circuits are studied by simulation. The influence factors including standard cell types and circuit operations have been investigated accordingly. Moreover, the exploration of ZTD point with different delay metrics is discussed, which is the basis of the selection of ZTD point at standard cell level. The ZTD point changes due to the five PVT corners and the selection of the ZTD point under these PVT corners are studied. Taking three kinds of delay chains and benchmark circuits as an example, the ZTD point in the critical path of the circuit is further investigated. The simulation results confirm that utilizing the ZTD voltage during the design of digital circuits can provide a better temperature-resistant solution, which makes sense for temperature immunity digital applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"77-83"},"PeriodicalIF":2.0,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization, Analysis, and Modeling of Long-Term RF Reliability and Degradation of SiGe HBTs for High Power Density Applications","authors":"Christoph Weimer;Gerhard G. Fischer;Michael Schröter","doi":"10.1109/TDMR.2023.3343503","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3343503","url":null,"abstract":"This paper aims at determining RF operating limits of SiGe HBTs. Long-term stress tests consisting of RF large-signal stress and periodic measurements of small-signal parameters are performed. Reliable dynamic large-signal transistor operation is demonstrated beyond conventional static safe operating limits. In addition, RF operating limits are identified and degradation of SiGe HBTs accelerated by extreme RF stress is systematically characterized, analyzed and modeled. RF-stress-caused degradation is shown to significantly affect the collector current and demonstrated to be different from electrothermal breakdown caused by DC stress. A modeling approach for estimating SiGe HBT degradation under RF large-signal operating conditions is proposed and shown to agree very well with experimental data.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"20-32"},"PeriodicalIF":2.0,"publicationDate":"2023-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2023 Index IEEE Transactions on Device and Materials Reliability Vol. 23","authors":"","doi":"10.1109/TDMR.2023.3341241","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3341241","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"627-646"},"PeriodicalIF":2.0,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10355055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138577947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of the Long-Term Reliability of a Velostat-Based Flexible Pressure Sensor Array for 210 Days","authors":"Anis Fatema;Shirley Chauhan;Mohee Datta Gupta;Aftab M. Hussain","doi":"10.1109/TDMR.2023.3340711","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340711","url":null,"abstract":"Pressure sensors are subjected to continuous force and stress that may affect the operation of the sensor in the long run. Reliability is a crucial factor that must be considered when designing and fabricating any sensor. It is essential to test the material used in the sensor to assess the reliability of the complete product. In this work, we report the long-term reliability of a flexible pressure sensor mat using a carbon-impregnated polymer, velostat, which is a flexible, light, and thin polymer composite material with piezoresistive properties. We focus on the analysis of the performance of a flexible pressure sensor array under long-term and repeated loading. Tests were performed every fortnight for 210 days. We have observed that the material characteristics of the velostat material change on repeated application of pressure up to a certain time frame. For a given loading, once the material settles, the change in resistance of the material becomes consistent for a given application of pressure. We have also analyzed the changes in the parameters associated with the 2-parameter model, and have analyzed the effect of crosstalk on the sensor matrix for different pitch lengths to select the best pitch that will give us the minimum crosstalk. We have observed that the error rate of the sensor pixels decreased by 53 percentage points in 210 days. The results obtained from the experimental tests for reliability reveal a practical possibility of implementing velostat-based pressure sensors in wearable and healthcare devices and provide steps to take while calibrating an as-fabricated velostat-based sensor.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"41-48"},"PeriodicalIF":2.0,"publicationDate":"2023-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation and Reliability Modeling of EM Robustness of Voltage Regulators Based on ADT: An Approach and a Case Study","authors":"Jaber Al Rashid;Mohsen Koohestani;Laurent Saintis;Mihaela Barreau","doi":"10.1109/TDMR.2023.3340426","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340426","url":null,"abstract":"This paper presents an approach to develop degradation and reliability models of analog integrated circuit (IC) voltage regulators based on the long-term evolution of the electromagnetic compatibility (EMC) performance degradation due to the stress time-dependent accelerated degradation test (ADT). The ADT plan is designed and conducted on six samples of both UA78L05 and L78L05 ICs placed inside a climatic chamber combining both the thermal step-stress (i.e., 70-110 °C) and constant electrical overstress (i.e., 9 and 12 V) conditions for a total stress duration of 950 hours. All the selected UA78L05 and L78L05 samples are subjected to the direct power injection (DPI) measurement test under nominal conditions in order to characterize their immunity to electromagnetic interference (EMI). The statistical degradation data (i.e., the average injected power) of the aged samples is computed across the entire DPI frequency range for a variety of stress time duration. The proposed log-linear accelerated life-stress test (ALT) model is combined with the Weibull unreliability distribution function model to estimate the failure lifetime data against the applied voltage stress at three different failure threshold criterion. At various constant voltage overstress and threshold constraints, the lifetime reliability performance parameters (i.e., time-to-failure, probability of failure, model constants) of the tested device under tests (DUTs) were evaluated based on the measured degradation data. It is demonstrated that, for a limited number of samples under the combined influence of thermal step-stress with voltage overstress conditions, the proposed reliability model predicts with a very acceptable accuracy the lifetime reliability of both UA78L05 and L78L05 tested ICs, developed based on the conducted immunity degradation data. The physics-based modeling approach is utilized to develop the model for the degradation paths based on the observed monotonic degradation of the measured degradation data as well as the conditions of the thermal step-stress ADT. In order to estimate the unknown parameters of the developed degradation model, the maximum likelihood estimation (MLE) method is combined with a genetic optimisation algorithm.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"2-13"},"PeriodicalIF":2.0,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Comprehensive Evaluation of Time-Dependent Dielectric Breakdown of CuAl₂ on SiO₂ for Advanced Interconnect Application","authors":"Toshihiro Kuge;Masataka Yahagi;Junichi Koike","doi":"10.1109/TDMR.2023.3340231","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340231","url":null,"abstract":"The intermetallic compound CuAl2 is a promising alternative to advanced Cu interconnections because of low electrical resistivity, short electron mean free path, good electromigration reliability, and good gap-filling property. In this study, to further examine the feasibility of CuAl2 interconnects for future technology node, a comprehensive study of the time-dependent dielectric breakdown (TDDB) was conducted on CuAl2 and compared with NiAl and Cu/TaN. The self-formation of a proper thickness of an AlOx interface layer by reaction with SiO2 brought about excellent TDDB reliability in CuAl2/SiO2. Voltage ramp test was also carried out to understand the electron transport mechanism in CuAl2 stressed under the same condition as that of the TDDB test. Leakage current versus voltage relation revealed the Cu ion drift into SiO2, which gave rise to Schottky emission as an electron transport mechanism across SiO2 and the accumulation of Cu ions eventually led to TDDB failure.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"14-19"},"PeriodicalIF":2.0,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TDMR.2023.3338877","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3338877","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"626-626"},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10346022","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138502124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}