IEEE Transactions on Device and Materials Reliability最新文献_第8页

Mitigating the Process Variations in Negative Capacitance Junctionless Device and Circuit 减小负电容无结器件和电路的工艺变化

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-02-26 DOI: 10.1109/TDMR.2026.3668390

Ruma S. R.;Manish Gupta

{"title":"Mitigating the Process Variations in Negative Capacitance Junctionless Device and Circuit","authors":"Ruma S. R.;Manish Gupta","doi":"10.1109/TDMR.2026.3668390","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3668390","url":null,"abstract":"Through well-calibrated simulations, this work presents a comprehensive analysis of process-induced variations in on-current (<inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula>), off-current (<inline-formula> <tex-math>$I_{mathrm {OFF}}$ </tex-math></inline-formula>), and threshold voltage (<inline-formula> <tex-math>$V_{mathrm {th}}$ </tex-math></inline-formula>) for negative capacitance (NC) junctionless (JL) transistors designed on bulk substrate. The performance and variability metrics are benchmarked against SOI-based NCJL transistors. The results reveal a significant reduction in <inline-formula> <tex-math>$sigma (I_{mathrm {ON}})$ </tex-math></inline-formula>, <inline-formula> <tex-math>$sigma (I_{mathrm {OFF}})$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$sigma (V_{mathrm {th}})$ </tex-math></inline-formula> due to the variation in geometrical device parameters in bulk NCJL devices. The outperformance is primarily due to the shift in the conduction channel towards the front surface, which enhances the effectiveness of the negative capacitance effect in bulk NCJL device. In addition, the lower variability observed in bulk NCJL devices translates into improved noise margin (<italic>NM) and reduced process-induced <italic>NM fluctuations in inverter circuits. Results reported for the first time demonstrate the enhanced device- and circuit-level performance of bulk NCJL transistors in comparison to their SOI counterparts.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"503-509"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148510328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental Investigation Into Ageing Mechanisms and Behavior Prediction Model of Flexible Electronic Substrates Under Temperature–Humidity–Bending Conditions 温湿弯曲条件下柔性电子衬底老化机理及行为预测模型的实验研究

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-16 DOI: 10.1109/TDMR.2026.3674172

Zhifeng He;Kaixuan Wang;Mingmin Zhu;Haibin Zhu;Hao-Miao Zhou

{"title":"Experimental Investigation Into Ageing Mechanisms and Behavior Prediction Model of Flexible Electronic Substrates Under Temperature–Humidity–Bending Conditions","authors":"Zhifeng He;Kaixuan Wang;Mingmin Zhu;Haibin Zhu;Hao-Miao Zhou","doi":"10.1109/TDMR.2026.3674172","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3674172","url":null,"abstract":"Flexible electronic substrates, as the critical constituent of flexible electronic devices and systems, are essential for component interconnection and overall structural flexibility. During service, they are routinely subjected to diverse temperature–humidity environments and static bending conditions. These external factors progressively induce material ageing and deterioration of electrical interconnect performance. The actual occurrence of ageing in flexible electronic substrates was experimentally confirmed by subjecting them to accelerated ageing tests. Electrical resistance was employed as the ageing indicator. The influence mechanisms of temperature–humidity conditions, bending radius, and specimen specifications on the ageing process were systematically quantified. A physics-based characterization model for the ageing effect was subsequently derived. A hybrid physics-informed neural network (PINN) was then constructed and trained to predict resistance evolution. The model achieved a mean relative error of 0.02% against measured data, demonstrating its validity and high accuracy. This work provides a direct quantitative basis for reliability assessment and performance-degradation prediction of flexible-substrate-based electronic devices. It thus potentially offers valuable support for ensuring and enhancing product quality and operational lifetime.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"475-484"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148514354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comparative Review of Junction Temperature Monitoring for SiC-Based Power Semiconductor Devices 基于sic的功率半导体器件结温监测比较综述

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-04 DOI: 10.1109/TDMR.2026.3689949

Guangjie Zhu;Xiangshun Li;Song Xiong;Cheng Wang

{"title":"A Comparative Review of Junction Temperature Monitoring for SiC-Based Power Semiconductor Devices","authors":"Guangjie Zhu;Xiangshun Li;Song Xiong;Cheng Wang","doi":"10.1109/TDMR.2026.3689949","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3689949","url":null,"abstract":"Silicon carbide power devices, representing third-generation semiconductors, are widely used in the areas of industrial control, rail transportation, electric vehicles, and renewable energy. As crucial components of power electronic systems, their reliability is vital to the safe operation of entire systems. Temperature is a critical factor affecting device reliability, and junction temperature serves as a key indicator reflecting the thermal state of the device. Accurate monitoring of junction temperature is therefore essential for tracking device conditions and assessing reliability. This paper provides a comparative review of advances in junction temperature monitoring for silicon carbide-based power devices, systematically analyzing four primary methods: thermal network model, temperature-sensitive electrical parameter, physical contact sensing, and non-contact optical methods. The principles, advantages and limitations as well as applicable situations of each method are analyzed in detail. Furthermore, the evolutionary trajectory of the estimation methods and associated validation techniques are summarized. Finally, challenges and future prospects for junction temperature monitoring for silicon carbide-based power devices are presented. This review concludes that temperature-sensitive electrical parameters method represent the most promising technique for future junction temperature monitoring. Nevertheless, significant challenges persist, particularly in relation to aging-induced coupling and the complexities of accurate parameter extraction. The purpose of this review is to provide helpful theoretical support and methodological guidance to researchers in related fields.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"409-434"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148517251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of Varying Degrees of Power Cycling Aging on Short-Circuit Ruggedness in 1.2-kV SiC MOSFET 功率循环老化程度对1.2 kv SiC MOSFET短路坚固性的影响

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-12 DOI: 10.1109/TDMR.2026.3673394

Pengkai Wang;Yuan Chen;Yangtao Long;Hu He;Junhui Li

引用次数: 0

Avalanche Failure Mechanisms of 1200-V/40-A 4H-SiC Junction Barrier Schottky Diodes With Various Epilayer Defects 具有不同涂层缺陷的1200-V/40-A 4H-SiC结势垒肖特基二极管雪崩失效机理

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-23 DOI: 10.1109/TDMR.2026.3676812

Jinlan Li;Yan Xu;Huaren Sheng;Quanzhi Chen;Ling Dong;Yiming Shi;Yulin Wang;Liming Zhou;Yuan Xu

引用次数: 0

Study of the Degradation in p-GaN Gate HEMTs Under Gate Pulse Stress by Transient Current Analysis 用瞬态电流分析研究p-GaN栅极hemt在栅极脉冲应力下的退化

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-06 DOI: 10.1109/TDMR.2026.3671275

Shijie Pan;Shanhai Gu;Shiwei Feng;Yamin Zhang;Xuan Li;Xiaozhuang Lu;Maran Wu

{"title":"Study of the Degradation in p-GaN Gate HEMTs Under Gate Pulse Stress by Transient Current Analysis","authors":"Shijie Pan;Shanhai Gu;Shiwei Feng;Yamin Zhang;Xuan Li;Xiaozhuang Lu;Maran Wu","doi":"10.1109/TDMR.2026.3671275","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3671275","url":null,"abstract":"This work investigates the trap-induced degradation in p-GaN gate HEMTs under gate pulse stress via transient current analysis. Electrical measurements demonstrate a positive threshold voltage shift and a reduction in drain current with prolonged bipolar pulse stress. Using the transient current method combined with Bayesian deconvolution, three distinct trap levels designated DP1 to DP3 are identified, whose amplitudes grow consistently with stress time. To clarify the underlying mechanism, bipolar and unipolar pulse stresses are compared at varying frequencies. The threshold voltage shift increases with frequency under bipolar stress but decreases under unipolar stress, confirming that bipolar stress enhances trap density rather than causes transient trap filling. Furthermore, DP1 and DP3 exhibit the significant enhancement in amplitudes, indicating their location near the gate interface where they are vulnerable to pulse-induced carrier injection. Temperature-dependent measurements further confirm that the degradation stems from the density increase of pre-existing traps, with no new trap levels generated. These findings provide critical insight into trap-induced degradation in p-GaN HEMTs, supporting reliability optimization in switching applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"541-548"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148511057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Post-Metallization Annealing on the Reliability of Barrierless Mo Word Lines 金属化后退火对无障碍钼字线可靠性的影响

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-11 DOI: 10.1109/TDMR.2026.3673011

D. Tierno;H. Bana;M. H. van der Veen;Y. Jeong;S. Decoster;G. Van den Bosch;J. W. Maes;M. Rosmeulen

{"title":"Impact of Post-Metallization Annealing on the Reliability of Barrierless Mo Word Lines","authors":"D. Tierno;H. Bana;M. H. van der Veen;Y. Jeong;S. Decoster;G. Van den Bosch;J. W. Maes;M. Rosmeulen","doi":"10.1109/TDMR.2026.3673011","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3673011","url":null,"abstract":"Post-metallization annealing (PMA) offers significant resistivity improvements for molybdenum word lines (WLs) in 3D NAND Flash, but its impact on device reliability remains unclear. This work systematically evaluates PMA effects using planar capacitors designed for high-temperature processing, comparing Mo deposited by PVD and ALD on PECVD and PEALD SiO2 under H2 (<inline-formula> <tex-math>$650~^{circ }$ </tex-math></inline-formula>C) and N2 (<inline-formula> <tex-math>$750~^{circ }$ </tex-math></inline-formula>C) annealing. Our electrical characterization reveals trap-assisted Fowler-Nordheim tunneling as the dominant conduction mechanism, with barrier heights significantly influenced by annealing conditions in PEALD SiO2. Time-dependent dielectric breakdown (TDDB) measurements at elevated temperatures confirm that no metal drift occurs even after high-temperature annealing. Failure is caused by a field-driven intrinsic dielectric breakdown, with no evidence of Mo-induced degradation. H2 annealing provides an optimal balance between resistivity improvement and interface quality. These findings establish a pathway for implementing barrierless Mo metallization in sub-30nm z-pitch 3D NAND devices, enabling further vertical scaling while maintaining reliability requirements for both programming and reading operations.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"451-458"},"PeriodicalIF":2.7,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148512519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Irradiation-Induced Charges Assist SiC/SiO2 Interface Trap Generation Under Gate Switching Stress in SiC MOSFETs 辐照诱导电荷在SiC mosfet栅极开关应力下促进SiC/SiO2界面陷阱的产生

IF 2.3 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-04-27 DOI: 10.1109/TDMR.2026.3687417

Jiahao Hu;Xiaochuan Deng;Chunhua Li;Xuan Li;Bo Zhang

{"title":"Irradiation-Induced Charges Assist SiC/SiO2 Interface Trap Generation Under Gate Switching Stress in SiC MOSFETs","authors":"Jiahao Hu;Xiaochuan Deng;Chunhua Li;Xuan Li;Bo Zhang","doi":"10.1109/TDMR.2026.3687417","DOIUrl":"https://doi.org/10.1109/TDMR.2026.3687417","url":null,"abstract":"The degradation of threshold voltage (<inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula>) induced by gate switching stress (GSS) in Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) is a critical reliability concern in power applications. Locally enhanced electric field and recombination-enhanced defect reactions (REDRs) are the two main mechanisms proposed to explain this degradation. This paper analyzes the degradation behavior of SiC MOSFETs subjected to GSS after total ionizing dose irradiation to gain deeper insight into these degradation mechanisms. By extracting the interface state density (<inline-formula> <tex-math>$D_{text {it}}$ </tex-math></inline-formula>) and separating the interface trapped charge (<inline-formula> <tex-math>$N_{text {it}}$ </tex-math></inline-formula>) and oxide trapped charge (<inline-formula> <tex-math>$N_{text {ot}}$ </tex-math></inline-formula>) from the subthreshold characteristics, it is found that the degradation mechanism under pure GSS is mainly governed by locally enhanced electric field, whereas GSS applied after +15 V gate-bias TID irradiation activates REDRs, generating new interface traps. The main reason is that irradiation-induced interface trapped charges assist electron-hole recombination during GSS, releasing more energy to trigger REDRs. This work contributes to the understanding of <inline-formula> <tex-math>$V_{text {th}}$ </tex-math></inline-formula> degradation in SiC MOSFETs under high-frequency switching and provides important guidance for improving their long-term reliability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"26 2","pages":"629-636"},"PeriodicalIF":2.3,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148214910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Measurement and Modeling of Bond Wire Degradation in TO-Packaged SiC MOSFETs to封装SiC mosfet中键合线退化的测量与建模

IF 2.7 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-05 DOI: 10.1109/TDMR.2026.3690502

Zhongyuan Chen;Hongji Li;Meiting Cui;Rui Jin;Li Ran

引用次数: 0

Impact of Substrate Connection on Dynamic-RON Drift of 650 V Normally-Off Monolithic Bidirectional AlGaN/GaN HEMT 衬底连接对650 V常关单片双向AlGaN/GaN HEMT动态漂移的影响

IF 2.3 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2026-06-01 Epub Date: 2026-03-06 DOI: 10.1109/TDMR.2026.3671620

Marcello Cioni;Alessandro Chini;Giacomo Cappellini;Giovanni Giorgino;Nuri Said;Maurizio Moschetti;Cristina Miccoli;Tariq Wakrim;Alessandro Contarino;Adriano Abbisogni;Antonio Pizzardi;Santo Smerzi;Maria Eloisa Castagna;Aurore Constant;Ferdinando Iucolano

引用次数: 0