IEEE Transactions on Device and Materials Reliability最新文献

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Call for Nominations Editor-in-Chief IEEE Transactions on Device and Materials Reliability 征集 IEEE《器件与材料可靠性》杂志主编提名
IF 2 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3369791
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引用次数: 0
Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers 半导体制造设计 (DFM) 特刊 联合征稿
IF 2 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3371835
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引用次数: 0
TechRxiv: Share Your Preprint Research with the World! TechRxiv:与世界分享您的预印本研究成果!
IF 2 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3374489
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引用次数: 0
Blank Page 空白页
IF 2 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3366775
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引用次数: 0
Optimization of 3-D IC Routing Based on Thermal Equalization Analysis 基于热均衡分析的 3D 集成电路布线优化
IF 2.5 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3374231
Le Liu;Fengjuan Wang;Xiangkun Yin;Chuanhong Sun;Xiang Li;Yue Li;Ningmei Yu;Yuan Yang
{"title":"Optimization of 3-D IC Routing Based on Thermal Equalization Analysis","authors":"Le Liu;Fengjuan Wang;Xiangkun Yin;Chuanhong Sun;Xiang Li;Yue Li;Ningmei Yu;Yuan Yang","doi":"10.1109/TDMR.2024.3374231","DOIUrl":"10.1109/TDMR.2024.3374231","url":null,"abstract":"Three-dimensional integrated circuits (3D ICs) offer performance advantages due to their reduced wiring overcomes the drawbacks of 2D IC and a vital structure called through-silicon via (TSV) is used to connect the adjacent layers vertically. However, the 3D structure will inevitably lead to thermal issues, and poor routing management in 3D ICs will lead to the increase of thermal stress in 3D IC chips and the deterioration of system stability. In this paper, based on thermal equalization, the chip-silicon interposer-printed circuit board (PCB) assembly structure is simulated and analyzed combined with layout design to investigate the impact of layout, solder ball selection, and TSV layout on the routing of 3D IC layout. The simulation results demonstrate our routing optimization method achieves optimized thermal stress, less large local deformation, reduced temperature, and higher system stability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"250-259"},"PeriodicalIF":2.5,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140075691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Transactions on Device and Materials Reliability Information for Authors IEEE 《器件与材料可靠性》期刊为作者提供的信息
IF 2 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3366730
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引用次数: 0
IEEE Transactions on Device and Materials Reliability Publication Information IEEE 器件与材料可靠性期刊》出版信息
IF 2 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-08 DOI: 10.1109/TDMR.2024.3366774
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引用次数: 0
Extraction of Charge Trapping Kinetics of Defects From Single-Defect Measurements 从单缺陷测量中提取缺陷的电荷捕获动力学
IF 2.5 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-03-01 DOI: 10.1109/TDMR.2024.3395907
Michael Waltl;Bernhard Stampfer;Tibor Grasser
{"title":"Extraction of Charge Trapping Kinetics of Defects From Single-Defect Measurements","authors":"Michael Waltl;Bernhard Stampfer;Tibor Grasser","doi":"10.1109/TDMR.2024.3395907","DOIUrl":"10.1109/TDMR.2024.3395907","url":null,"abstract":"Charge trapping at oxide defects poses a serious reliability concern in MOS transistors. For scaled technology nodes, the impact of charge-trapping events on the device behavior becomes even more severe. These events can be seen as discrete steps in the device current, allowing for single-defect analysis. In this context, random telegraph noise (RTN) analysis and time-dependent defect spectroscopy (TDDS) have become very popular in exploring the physical origin of charge trapping at single defects. To improve the accuracy of single-defect analysis, we conduct a Monte Carlo analysis of trap occupancy, enabling us to extract information about the charge emission time of fixed oxide traps from charge capture time data recorded under different stress conditions. The newly gained knowledge is beneficial for accurately calibrating defect models used to explain the charge-trapping dynamics of defects.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"168-173"},"PeriodicalIF":2.5,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10517280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140832517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure Mechanism and Predictive Modeling for Microbump Interconnects Drop Life Under Diverse Impact Angles in Advanced Packaging 先进封装中不同冲击角度下微凸块互连器件滴落寿命的失效机理和预测模型
IF 2.5 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-02-27 DOI: 10.1109/TDMR.2024.3370631
Yangtao Long;Mingtao Lv;Hu He
{"title":"Failure Mechanism and Predictive Modeling for Microbump Interconnects Drop Life Under Diverse Impact Angles in Advanced Packaging","authors":"Yangtao Long;Mingtao Lv;Hu He","doi":"10.1109/TDMR.2024.3370631","DOIUrl":"10.1109/TDMR.2024.3370631","url":null,"abstract":"With the advancement of Moore’s Law, the impact reliability of solder joints has emerged as a critical concern due to the reduction in their size. The board-level drop test, based on the JEDEC standard, is widely employed by researchers to assess the impact performance of electronic packages. Typically, these tests are conducted with boards placed horizontally. However, real-world service environments involve impacts at various angles that can lead to different failure mechanisms in solder joints. In this study, we investigate the impact reliability of microbump interconnect structures under different impact angles. By considering plastic strain analysis, we demonstrate that drop impacts at other angles can be equivalently represented by the scenario with drop angle \u0000<inline-formula> <tex-math>$alpha =$ </tex-math></inline-formula>\u0000 0° impact. Subsequently, we analyze the failure mechanism of microbumps during drop tests and propose a predictive model for their drop life under varying impact angles. Our results indicate that as the drop angle increases, there is a transition in the driving force for microbump failures from tensile and compressive stress to shear stress. The proposed life prediction model exhibits an error rate below 25% and effectively forecasts the drop life of microbumps in advanced packaging.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"241-249"},"PeriodicalIF":2.5,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140003582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Multicrystalline Si Solar Cell Improvement Using Laser-Beam-Induced Current Technique 利用激光束感应电流技术分析多晶矽太阳能电池的改进情况
IF 2.5 3区 工程技术
IEEE Transactions on Device and Materials Reliability Pub Date : 2024-02-19 DOI: 10.1109/TDMR.2024.3367353
T. Takeshita;E. Murakami
{"title":"Analysis of Multicrystalline Si Solar Cell Improvement Using Laser-Beam-Induced Current Technique","authors":"T. Takeshita;E. Murakami","doi":"10.1109/TDMR.2024.3367353","DOIUrl":"10.1109/TDMR.2024.3367353","url":null,"abstract":"The improvement of an mc-Si solar cell through reverse bias and high temperature (BT) aging was investigated using laser beam-induced current (LBIC) and electroluminescence (EL) techniques. We demonstrated that the dark current of the cell decreased with increasing aging time, which led to an increase in the maximum power after BT aging. The improvement in the maximum power was presumed to be due to a reduction in the shunt current in the equivalent circuit model, and we found that the recombination centers in the vicinity of the surface decreased with BT aging. Applying a reverse bias and a high temperature successfully improved the solar cells.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"219-224"},"PeriodicalIF":2.5,"publicationDate":"2024-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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