IEEE Transactions on Device and Materials Reliability最新文献_第8页

Special Issue on Intelligent Sensor Systems for the IEEE Journal of Electron Devices 电气和电子工程师学会电子器件期刊》智能传感器系统特刊

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405612

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405820

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IEEE Transactions on Device and Materials Reliability Information for Authors IEEE 《器件与材料可靠性》期刊为作者提供的信息

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405819

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Guest Editorial TDMR IIRW Special Section 特约编辑 TDMR IIRW 特辑

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3407548

Charles LaRow

{"title":"Guest Editorial TDMR IIRW Special Section","authors":"Charles LaRow","doi":"10.1109/TDMR.2024.3407548","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3407548","url":null,"abstract":"The IEEE International Integrated Reliability Workshop (IIRW) is a distinctive event which brings together reliability researchers, professionals, and students from around the globe to a common forum for lively discussions, wonderful technical presentations, and beautiful scenery for 4 days and nights. The event takes place every year at Fallen Leaf Lake in South Lake Tahoe, CA, USA, where attendees are housed within a secluded camp with informal meeting spaces and access to boats, trails, and many other outdoor activities. The scope of content centers around hot topics in, novel techniques for, and general knowledge on semiconductor reliability research and industry challenges. Talks on transistor and front-end-of-the-line (FEOL) reliability, bias temperature instability (BTI), hot carrier (HC), gate dielectric time-dependent dielectric breakdown (TDDB), back-end-of-the-line (BEOL) reliability, Interconnect TDDB, electro-migration (EM), circuit reliability, packaging reliability, conventional and emerging memory reliability, failure analysis (FA), wafer-level reliability (WLR), among other topic are presented. The key focus areas at IIRW 2023 were Advanced node scaling solutions (FEOL/MOL/BEOL), circuit reliability (device-circuit degradation and aging).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"159-160"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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IEEE Transactions on Device and Materials Reliability Publication Information IEEE 器件与材料可靠性期刊》出版信息

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3405818

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Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers 半导体制造设计 (DFM) 特刊联合征稿

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-20 DOI: 10.1109/TDMR.2024.3412348

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An Empirical Study on Fault Detection and Root Cause Analysis of Indium Tin Oxide Electrodes by Processing S-Parameter Patterns 通过处理 S 参数模式进行氧化铟锡电极故障检测和根本原因分析的实证研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-17 DOI: 10.1109/TDMR.2024.3415049

Tae Yeob Kang;Haebom Lee;Sungho Suh

{"title":"An Empirical Study on Fault Detection and Root Cause Analysis of Indium Tin Oxide Electrodes by Processing S-Parameter Patterns","authors":"Tae Yeob Kang;Haebom Lee;Sungho Suh","doi":"10.1109/TDMR.2024.3415049","DOIUrl":"10.1109/TDMR.2024.3415049","url":null,"abstract":"In the field of optoelectronics, indium tin oxide (ITO) electrodes play a crucial role in various applications, such as displays, sensors, and solar cells. Effective fault diagnosis and root cause analysis of the ITO electrodes are essential to ensure the performance and reliability of the devices. However, traditional visual inspection is challenging with transparent ITO electrodes, and existing fault diagnosis methods have limitations in determining the root causes of the defects, often requiring destructive evaluations and secondary material characterization techniques. In this study, a fault diagnosis method with root cause analysis is proposed using scattering parameter (S-parameter) patterns, offering early detection, high diagnostic accuracy, and noise robustness. A comprehensive S-parameter pattern database is obtained according to various defect states of the ITO electrodes. Deep learning (DL) approaches, including multilayer perceptron (MLP), convolutional neural network (CNN), and transformer, are then used to simultaneously analyze the cause and severity of defects. Notably, it is demonstrated that the diagnostic performance under additive noise levels can be significantly enhanced by combining different channels of the S-parameters as input to the learning algorithms, as confirmed through the t-distributed stochastic neighbor embedding (t-SNE) dimension reduction visualization of the S-parameter patterns.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"380-389"},"PeriodicalIF":2.5,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Modeling of Threshold Voltage Degradation of 22nm FD-SOI nMOSFETs Under Dynamic Voltage Scaling 动态电压扩展下 22 纳米 FD-SOI nMOSFET 的阈值电压衰减建模

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-13 DOI: 10.1109/TDMR.2024.3414181

Yibo Hu;Hao Ge;Zhipeng Ren;Yizhe Yin;Jing Chen

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Dynamic Reliability Assessment of Vertical GaN Trench MOSFETs With Thick Bottom Dielectric 厚底电介质垂直氮化镓沟槽 MOSFET 的动态可靠性评估

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-06-03 DOI: 10.1109/TDMR.2024.3408293

Yu Zhang;Renqiang Zhu;Haolan Qu;Yitian Gu;Huaxing Jiang;Kei May Lau;Xinbo Zou

{"title":"Dynamic Reliability Assessment of Vertical GaN Trench MOSFETs With Thick Bottom Dielectric","authors":"Yu Zhang;Renqiang Zhu;Haolan Qu;Yitian Gu;Huaxing Jiang;Kei May Lau;Xinbo Zou","doi":"10.1109/TDMR.2024.3408293","DOIUrl":"10.1109/TDMR.2024.3408293","url":null,"abstract":"Dynamic stability of quasi-vertical GaN trench MOSFETs featuring a thick bottom dielectric (TBD) is thoroughly investigated. Degradation in forward drain current was observed as applying gate or drain stressing voltage, and further studied by time-resolved measurements. The drain current of the device can be maintained at 79%, compared to 61% of a reference device without TBD. Meanwhile, repeated switching tests conducted within a short on-state time demonstrate that the current collapse is confined to 10% after 500 switching cycles. The current collapse is related to electron capture at the dielectric/GaN interface, and the introduction of TBD reduces the electric field within the dielectric layer and suppresses the capture process of traps. Positive gate bias-induced threshold instability of the device with and without TBD is investigated. For the device with TBD, a small positive threshold voltage shift of 1 V is obtained. In addition, the effect of drain stressing voltage on devices is also revealed. High-resolution drain current transient spectroscopy displays the drain current reduction, attributing the degradation to captured electrons in the n--GaN layer. A capture activation energy of 0.26 eV is revealed by deep level transient spectroscopy. These findings reveal the efficacy of TBD inclusion in improving gate stability of GaN MOSFETs and underscore the critical importance of high-quality epitaxial growth for ensuring the stability of vertical devices. The stability characterization serves as a valuable reference for the development of reliable quasi-vertical GaN MOSFET devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"358-364"},"PeriodicalIF":2.5,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators 基于随机电报噪声的真正随机数生成器设计指南

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-04-29 DOI: 10.1109/TDMR.2024.3394576

Tommaso Zanotti;Alok Ranjan;Sean J. O’Shea;Nagarajan Raghavan;Ramesh Thamankar;Kin Leong Pey;Francesco Maria Puglisi

{"title":"Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators","authors":"Tommaso Zanotti;Alok Ranjan;Sean J. O’Shea;Nagarajan Raghavan;Ramesh Thamankar;Kin Leong Pey;Francesco Maria Puglisi","doi":"10.1109/TDMR.2024.3394576","DOIUrl":"10.1109/TDMR.2024.3394576","url":null,"abstract":"The development of a robust and secure hardware for the Internet of Things (IoT) and edge computing requires improvements in the existing low-power and low-cost hardware security primitives. Among the various available technologies, true random number generators (TRNGs) that leverage random telegraph noise (RTN) from nanoelectronics devices have emerged as effective solutions. However, the temporal instabilities in the RTN signal, such as the DC drift and temporary inhibition, are a few of the key reliability challenges for the TRNG circuits. In this study, we have utilized experimental RTN data collected from the commonly used gate dielectrics, including silicon dioxide (SiO2), hafnium dioxide (HfO2), and 2D crystalline hexagonal boron nitride (h-BN) to identify the crucial reliability challenges for RTN-based TRNG circuits. We have analyzed the impact of RTN instabilities and of circuit parameters on the output randomness and propose reliability aware design guidelines. Finally, we design and simulate an RTN-based TRNG circuit using a 130 nm CMOS technology and evaluate its reliability at the circuit level.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"184-193"},"PeriodicalIF":2.5,"publicationDate":"2024-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140832466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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