IEEE Transactions on Device and Materials Reliability最新文献

{"title":"Influence of Hot Carrier Degradation on Total Ionizing Dose in Bulk I/O-FinFETs","authors":"Ruxue Yao;Hongliang Lu;Yuming Zhang;Yutao Zhang;Jing Qiao;Jing Sun;Mingzhu Xun;Gang Yu","doi":"10.1109/TDMR.2024.3431633","DOIUrl":"10.1109/TDMR.2024.3431633","url":null,"abstract":"Electronic components operating in aerospace environments face a variety of reliability issues. The total ionization dose (TID) degradation mechanism of bulk I/O-FinFETs and the influence of hot carrier degradation (HCD) on TID irradiation are investigated in this paper. Devices under ON/TG/OFF bias conditions were irradiated to 2 Mrad (Si). The nFinFETs show degradation of threshold voltage, subthreshold swing and off-state leakage current. An increase in peak transconductance and on-state current was also observed in the nFinFETs. The TID response of nFinFETs is dominated by positively trapped charges in the gate oxide and shallow trench isolation (STI). For pFinFETs, radiation-induced hole-trapped charges leads to an increase in the threshold voltage and a decrease in the drive current. The worst degradation is observed when a high electric field is applied to the gate during irradiation. Post-stress irradiation results show that the HCD and TID degradation trends of the nFinFETs are opposite and have a mutual canceling effect, while the degradation trends of the pFinFETs are consistent and jointly deteriorate the device performance. Compared to the un-stressed devices, the TID damage of the pre-stressed devices is more drastic, especially for the nFinFETs. The stress-induced interface trapped charges increase the electric field in the gate oxide during subsequent irradiation, which causes more radiation-induced hole-trapped charges and exacerbate TID degradation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"456-462"},"PeriodicalIF":2.5,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141868453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs","authors":"Renze Yu;Saeed Jahdi;Konstantinos Floros;Ingo Lüdtke;Phil Mellor","doi":"10.1109/TDMR.2024.3431707","DOIUrl":"10.1109/TDMR.2024.3431707","url":null,"abstract":"Uneven electro-thermal conditions between parallel-connected devices can reduce the overall reliability of the power electronics systems, particularly during extreme cases such as short circuit. The current distribution between parallel devices is dynamically regulated during the transient and the degradation of devices is intertwined in the long run. To better understand the evolving patterns in the parallel configuration and to compare differences among various device structures, repetitive short circuit tests were conducted on planar, symmetrical double-trench, and asymmetrical trench SiC MOSFETs. Technology computer-aided design (TCAD) models were employed to analyze the evolution of current density and temperature profile between parallel devices. Test results indicate that the switching speed difference caused by gate resistance (Rg) mismatch leads to the asynchronous degradation of asymmetrical trench devices. The decreased threshold voltage (Vth) induce higher short circuit energy (Esc), forming a positive feedback for degradation. Besides, even if the current is dynamically shared between parallel SiC MOSFETs under different case temperature (Tcase), the initial temperature has a key impact on short-circuit reliability over Esc.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"437-447"},"PeriodicalIF":2.5,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141783340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Critical Working Conditions on Stability of Varistor Characteristics","authors":"Alija Jusić","doi":"10.1109/TDMR.2024.3430033","DOIUrl":"10.1109/TDMR.2024.3430033","url":null,"abstract":"In this paper, the results of the analysis of the influence of critical working conditions on stability of varistor characteristics are presented. Moreover, the paper offers both experimental and theoretical interpretation concerning the influence of temperature, operations’ time-number and the effect of neutron and gamma radiation on the stability of varistor characteristics. For the purpose of this paper an original measuring system of extremely low measurement uncertainty has been developed. Recording of volt-ampere, volt-ohm characteristics as well as varistor, breakdown voltage which was directly measured by a measuring system developed for that purpose, was carried out in the manner based on utilizing a single current pulse. Having analyzed the obtained results, it can be concluded that, when designing the insulation coordination at low or high voltage level, ambient environmental conditions (temperature variation) and functional aging in synergy with natural aging should be taken into account.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"448-455"},"PeriodicalIF":2.5,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Read Control Voltage Scheme for Reliability Enhancement of Flash-Based In-Memory Computing Architecture for Neural Network","authors":"Xinrui Zhang;Jian Huang;Xianping Liu;Baiqing Zhong;Zhiyi Yu","doi":"10.1109/TDMR.2024.3429662","DOIUrl":"10.1109/TDMR.2024.3429662","url":null,"abstract":"The storage reliability is critical for flash memory based computing in-memory (CIM) architecture for Convolutional Neural Network (CNN). In this paper, we constructed a CIM scheme based on the Nor Flash array (NFA). We conducted simulations to investigate the impact of threshold voltage distribution and drift of Flash memory cells on the recognition accuracy for various CNN architectures based on the CIM schemes. Based on the reliability study, we proposed a novel compensation scheme to effectively mitigate the impact of threshold voltage drift and evaluated the effectiveness of the proposed scheme by recognition accuracy evaluation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"422-427"},"PeriodicalIF":2.5,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance and Threshold Voltage Reliability of Quaternary InAlGaN/GaN MIS-HEMT on Si for Power Device Applications","authors":"Shivendra K. Rathaur;Cheng-Jun Ma;Abhisek Dixit;Ching-Ting Lee;Edward Yi Chang","doi":"10.1109/TDMR.2024.3429185","DOIUrl":"10.1109/TDMR.2024.3429185","url":null,"abstract":"In this study, we empirically explore the performance degradation of quaternary InAlGaN/AlN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) with a Gate Field Plate (GFP) structure under a Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) stresses. Both stress conditions (PBTI with V\u0000<inline-formula> <tex-math>${_{text {GS}}} = 10$ </tex-math></inline-formula>\u0000 V and NBTI with V\u0000<inline-formula> <tex-math>${_{text {GS}}} {=} -30$ </tex-math></inline-formula>\u0000 V) are applied. The experimental findings reveal a positive shift in threshold voltage (VTH), indicating the presence of a net negative charge beneath the gate area. However, we find distinct degradation dynamics for both stress experiments. During PBTI, the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift remains temperature independent, suggesting the generation of defects leading to electron trapping in the insulator. In NBTI, critical defects are identified, resulting in a permanent \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift with temperature dependence. Furthermore, the extracted activation energy (Ea) from Arrhenius plots in PBTI is determined to be 0.14 eV and 0.11 eV, highlighting the crucial role of shallow C-related traps governed by the Shockley-Read Hall (SRH) recombination process. In contrast, for NBTI, \u0000<inline-formula> <tex-math>${mathrm { E}}_{mathrm { a}} = 0.12$ </tex-math></inline-formula>\u0000 eV, indicating the involvement of surface traps and thermal-assisted de-trapping kinetics, leading to the generation of permanent defects. These results underscore the distinct dynamics of performance degradation phenomena in PBTI and NBTI involves different trap energies at different locations within the device structure.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"428-436"},"PeriodicalIF":2.5,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141720185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on Traps Dynamics & Negative Bias Stress in D-Mode GaN-on-Si Power MIS HEMTs Under High-Temperature","authors":"Shivendra K. Rathaur;Le Trung Hieu;Tsung-Ying Yang;Shang Hua Tsai;Wen Yu Lin;Abhisek Dixit;Edward Yi Chang","doi":"10.1109/TDMR.2024.3426526","DOIUrl":"10.1109/TDMR.2024.3426526","url":null,"abstract":"This experimental study investigates the traps dynamics and threshold voltage (VTH) shift mechanism under negative bias temperature stress for the GaN-on-Si Power MIS HEMTs on field plate design structure. Based on the experimental analysis, two distinct activation energies (Ea) have been identified under the specific reverse bias conditions of VGS= -30 V and VDS=0 V in a wide temperature range. Reverse bias stress experiments (up to 10 ks) show a positive VTH shift of ~1.6 V at room temperature due to the inversion of the charges at the interface between the insulator and AlGaN layer, resulting in net negative charge near the gate region. Subsequently, there is a decrease in VTH shift till \u0000<inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>\u0000 C because of the de-trapping of the inversion charges. This phenomenon shows a strong correlation with a thermally activated activation energy of (E\u0000<inline-formula> <tex-math>${_{text {a}}}~approx ~0.23$ </tex-math></inline-formula>\u0000 eV). Further, the shift in \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 turns negative when the temperature is raised to \u0000<inline-formula> <tex-math>$175~^{circ }$ </tex-math></inline-formula>\u0000 C, indicating the accumulation of electrons in the channel layer with activation energy (E\u0000<inline-formula> <tex-math>${_{text {a}}}~approx ~0.78$ </tex-math></inline-formula>\u0000 eV) attributed to the activation of nitrogen interstitials from the GaN buffer layer. Additionally, the recovery (up to 10 ks) behavior demonstrates the exponential-linear settlement of the traps to recover the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift. Moreover, nitrogen interstitials take more time to suppress the threshold voltage instabilities. These findings explain the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift mechanisms in GaN-on-Si Power MIS HEMTs under NBTI.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"414-421"},"PeriodicalIF":2.5,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141584947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Suppression of Total Dose Effects on the Performance of InAlGaN/GaN MIS-HEMT via Field Plate Implementation","authors":"Yi-En Chang-Chien;Chin-Han Chung;Chih-Yi Yang;Cheng-Jun Ma;Xiang-You Ye;You-Chen Weng;Edward Yi Chang","doi":"10.1109/TDMR.2024.3422326","DOIUrl":"10.1109/TDMR.2024.3422326","url":null,"abstract":"In this study, quaternary InAlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) aimed for power applications were exposed to 800 krad of Co\u0000<inline-formula> <tex-math>$^{60}~gamma $ </tex-math></inline-formula>\u0000-ray, and their response to total dose effects was recorded. For the irradiation process, devices with five gate-connected field plate schemes of field plate length (without field plate, \u0000<inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>\u0000 m, 4, \u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m, \u0000<inline-formula> <tex-math>$6~mu $ </tex-math></inline-formula>\u0000 m, \u0000<inline-formula> <tex-math>$8~mu $ </tex-math></inline-formula>\u0000 m) were tested under either a grounded state or a stressed state. It was discovered that the implementation of the field plate could successfully suppress the virtual gate phenomenon exacerbated by total dose effects. Post-irradiation analysis of the reverse characteristics also revealed that for devices irradiated under a stressed state, field plates could increase the device robustness against total dose effects impacting the electrical breakdown.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"407-413"},"PeriodicalIF":2.5,"publicationDate":"2024-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141575407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single-Event Burnout Effects of Complementary LDMOS Devices in High-Voltage Integrated Circuits","authors":"Chonghao Chen;Jiang Xu;Zhuojun Chen","doi":"10.1109/TDMR.2024.3420391","DOIUrl":"10.1109/TDMR.2024.3420391","url":null,"abstract":"Lateral diffused metal-oxide-semiconductor (LDMOS) devices are vulnerable to single-event burnout (SEB) in radiation environments, potentially leading to catastrophic failure in high-voltage integrated circuits (HVICs). Pulsed-laser experiments have demonstrated that the SEB triggering voltage of n-type LDMOS (nLDMOS) is significantly lower than that of p-type LDMOS (pLDMOS), which limits the applications of complementary LDMOS devices in aerospace electronic systems. This work investigates the SEB mechanism in both nLDMOS and pLDMOS through technology computer-aided design (TCAD) simulations. The analysis reveals that differences in the current gain of parasitic bipolar transistors and well resistance between pLDMOS and nLDMOS result in varying SEB triggering voltages. Additionally, a radiation-hardening technique is employed to improve the SEB triggering voltage of nLDMOS, aligning it closely with that of pLDMOS. This research provides insight into the design of radiation-hardened high-voltage integrated circuits, such as DC-DC converters and motor drivers, using a standard Bipolar-CMOS-DMOS (BCD) fabrication process.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"401-406"},"PeriodicalIF":2.5,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Prediction of Crack Initiation at Die Corner of Molded Underfill Flip-Chip Packages Under Thermal Load by New Criteria","authors":"G. C. Lyu;X. P. Zhang;M. B. Zhou;C. B. Ke;Y. W. Mai","doi":"10.1109/TDMR.2024.3420759","DOIUrl":"10.1109/TDMR.2024.3420759","url":null,"abstract":"The present study provides solutions for the stress and strain fields near the junction formed at the intersection of the inclusion and matrix interfaces under thermal load. It further explores how the non-singular stress terms influence the stress field near the corner of the interface between the molded underfill (MUF) and the die in a typical flip-chip (FC) package subjected to thermal load. The results obtained indicate that achieving a comprehensive understanding of the stress field requires consideration of the dominant singular stress terms, the regular stress term (the first non-singular stress term) and the I-stress term (the second non-singular stress term), so as to offer a theoretical basis for accurate evaluation of the reliability of integrated circuit packages.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"498-506"},"PeriodicalIF":2.5,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique","authors":"Feng Wei;Xiaole Cui;Qixue Zhang;Sunrui Zhang;Xiaoxin Cui;Xing Zhang","doi":"10.1109/TDMR.2024.3417961","DOIUrl":"10.1109/TDMR.2024.3417961","url":null,"abstract":"The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve its ability of recovering from the undesired node upset. However, the extra redundant transistors may increase the number of sensitive nodes in the SRAM cell, which decreases its capability of node-upset tolerance in turn. This work proposes an RHBD 14T SRAM cell and an RHBD 16T SRAM cell. Both the proposed SRAM cells only have two sensitive nodes. The proposed SRAM cells are able to recover from all the SNU cases. The layout harden technique is used to protect the proposed cells from SEMNU, and the blank of the hardened layout is reused so the proposed 14T and 16T SRAM cells consume the same area. Although the proposed cells have more transistors, the hardened layout areas of NS-10T/ PS-10T/ RHD-12T/ RHBD-10T/ RHBD-10T[VLSI]/ QUCCE-12T are respectively \u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.83times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.99times $ </tex-math></inline-formula>\u0000 larger than that of the proposed cells. The reason is that the layout harden technique is easier to be applied to the proposed cells because they only have two sensitive nodes.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"390-400"},"PeriodicalIF":2.5,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}