IEEE Transactions on Device and Materials Reliability最新文献

{"title":"Post-Breakdown IV Characteristics and Instabilities in Dense OTP Anti-Fuse Memories","authors":"Mattia Rossetti;Laura Atzeni;Rita Zappa","doi":"10.1109/TDMR.2025.3574776","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574776","url":null,"abstract":"Instability phenomena in dense one-time-programmable memories based on the breakdown of ultra-thin silicon dioxide layers are discussed. During stress at programming condition, cell IV characteristics are found to evolve between quasi-linear and highly non-linear characteristics. Extensive characterization of this instability is carried on as a function of stress duration and programming conditions to maximize post-breakdown current and guarantee values above the program-verify threshold. Read current instability is also observed during reading cycles and associated to a switching behavior between two or more states of the breakdown path that has been minimized by a proper cell design. Post-breakdown IV characteristics of the OTP cell are modeled based on the quantum-point contact model. Peculiar temperature dependence of the IV characteristics of programmed cells is nicely described by the proposed model.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"610-616"},"PeriodicalIF":2.3,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Board Level-Component Solder Joints Normalized Crack Severity Index of Solid-State Drive With Different Reliability Temperature Cycle Test Profiles","authors":"Erwan Basiron;Adlil Aizat Ismail;Azman Jalar;Maria Abu Bakar;Azman Ahmad","doi":"10.1109/TDMR.2025.3574447","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574447","url":null,"abstract":"In the realm of electronic device manufacturing, one persistent challenge is the lack of a universal TCT (Temperature Cycle Test) solder joints crack assessment that is suitable for all types of electronic components. This gap becomes particularly complex when multiple components are assembled into a single board. Therefore, this paper proposed an approach by normalizing the solder joints cracks, index <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> value as benchmarking value for solder joint cracks in components following TCT. This work used four types of components include controller, NAND, double data rate random-access memory (DDR-RAM) and power management integrated circuit (PMIC). All of these components subjected to three different TCT conditions (A) −40 to <inline-formula> <tex-math>$85~{^{^{circ }} }$ </tex-math></inline-formula>C, 10 mins soak, 12.5 mins ramp, 500 cycles, (B) 0 to <inline-formula> <tex-math>$100~{^{^{circ }} }$ </tex-math></inline-formula>C, 15 mins soak, 15 mins ramp, 750 cycles and (C) 0 to <inline-formula> <tex-math>$100~{^{^{circ }} }$ </tex-math></inline-formula>C, 15 mins soak, 15 mins ramp, 900 cycles to determine relative severity of the SSD design, and its critical components solder joint performance. Solder joints crack percentage is calculated from inspection post DnP and analysed to compare the severity. The normalize solder joints, index <inline-formula> <tex-math>$mathrm {{eta } }$ </tex-math></inline-formula>were calculated and used to analyse all the components post TCT. It was found that TCT profile C is more stringent with solder joint cracks <inline-formula> <tex-math>$4.1x$ </tex-math></inline-formula> higher than TCT profile A and <inline-formula> <tex-math>$2.5mathrm { x}$ </tex-math></inline-formula> higher than TCT profile B. The highest index <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> value of 5.2 from TCT profile C indicates that it is the most stringent of all tested TCT profiles, compared to TCT profile B at 2.67 and TCT profile A at 1.13. The findings from this study provide valuable insights into selecting effective TCT profiles, allowing for optimized testing procedures that save time and resources. This approach is particularly beneficial for specific components, including controller, NAND, DDR-RAM and PMIC packages. Furthermore, normalizing solder joint cracks using the index <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> value as a benchmarking metric can be applied to other types of electronic components.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"473-480"},"PeriodicalIF":2.3,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Phase Coarsening on Inhomogeneous Deformation and Fracture Behavior in Sn–Bi Solder Interconnects","authors":"Shuibao Liang;Han Jiang;Zhihong Zhong;Yaohua Xu;Saranarayanan Ramachandran","doi":"10.1109/TDMR.2025.3574560","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574560","url":null,"abstract":"With the increasing demand for emerging technologies like artificial intelligence and big data, the significance of advanced chip integration and packaging has grown considerably. Sn-Bi based solders have gained significant attention and have been explored for multi-layer stacked packaging, but they are prone to significant coarsening during service, and the effects of grain and phase anisotropy become more pronounced. These factors impact the performance and reliability of Sn-Bi solder interconnects. This study develops a numerical model to investigate microstructure coarsening in Sn-Bi solder bump interconnects, focusing on its effect on mechanical behavior and crack propagation. The simulated coarsening behavior aligns with experimental observations. Results show that, under shear loading, the Sn-rich phase experiences higher stress initially, while the Bi-rich phase bears greater stress later, leading to stress concentrations mainly in the Bi-rich phase or at the phase interfaces. Thermal aging exacerbates the uneven distribution of stress. Plastic strain is greater in the Sn-rich phase, and cracks primarily initiate and propagate in the Bi-rich phase. Coarsening accelerates crack growth, affecting the stress-strain response. This study provides insights into the effects of phase coarsening and inhomogeneous deformation in Sn-Bi solder interconnects, which may contribute to interconnect design and reliability analysis in three-dimensional packaging.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"585-593"},"PeriodicalIF":2.3,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resistive Defect Analysis and Fault Modeling of DICE Memory in Commercial 40-nm CMOS Technology","authors":"Yi Wang;Jiahao Yin;Yaohua Xu;Chunmei Hu","doi":"10.1109/TDMR.2025.3573599","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3573599","url":null,"abstract":"The complex architecture of double interlocked storage cell (DICE) static random access memories (SRAM), which consists of 12 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), presents challenges in manufacturing test. Manufacturing defects can cause faults in DICE SRAMs, and undetected faults may lead to test escapes, resulting in early in-field failures. These issues can prevent DICE SRAMs from meeting the applications requiring high quality in sectors such as aerospace. This paper proposes a new type of SEU fault for DICE SRAM, analyzing how physical defects influence its SEU resilience, which forms a new fault space together with parameter faults and functional faults.This paper presents a detailed analysis and fault modeling of resistive defects that may occur in DICE SRAMs and proposes a novel test algorithm to enhance fault coverage and reduce test escapes during manufacturing test. First, we define and classify the fault space, including functional faults, parameter faults, and single event upset (SEU) faults, and outline the methodology to validate faults within this space. Next, we inject resistive defects into the SPICE netlist of DICE SRAMs, conduct SPICE simulation, and inspect its corresponding behavior. Furthermore, through the analysis of the fault modeling results of DICE SRAMs and evaluating the test coverage and limitations of existing test solutions, we propose a new test algorithm. This results in a substantial increase in dynamic fault coverage from 20.57% to 28.37% and an overall improvement in fault coverage from 33.88% to 39.89% when compared to the March C+ algorithm, while reducing the possibility of test escape for parameter faults (including HSNM and RSNM faults) and SEU faults. In summary, the findings of the paper are effective in detecting the realistic faults in DICE SRAMs, thereby bolstering the effectiveness of DICE SRAMs test for critical applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"510-519"},"PeriodicalIF":2.3,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Shock Reliability of Silver-Sintered Bonding of Metal-Plated Aluminum Surfaces","authors":"Lisheng Wang;Gert Rietveld;Raymond J. E. Hueting","doi":"10.1109/TDMR.2025.3554369","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3554369","url":null,"abstract":"Silver (Ag) sintering is becoming more critical for future wide bandgap (WBG) power module substrate attachments. However, sintered Ag joints with plated aluminum (Al) heatsinks and directly bonded aluminum (DBA) substrates presently suffer from poor reliability. To resolve this problem, this work studies the reliability of plated (Nickel) Ni/Ag metallization on Al for sintered Ag joints and proposes a new plated Ni/Copper (Cu)/Ag metallization stack for improved reliability. The shear strength and thermal shock (TS) reliability of the sintered Ag joints for different metallization layers are studied, and microstructural and elemental analyses were performed to analyze the failure modes. The results show that the reliability of the sintered Ag joints by the traditional Ni/Ag metallization is rather limited because of poor adhesion between Ni and Ag. In contrast, the shear strength of the new Ni/Cu/Ag metallized sintered Ag joints is consistently above 40 MPa up to 500 TS cycles, with the dominant failure modes formed by Al/Ni delamination and cohesive failure. Preparing sintered Ag joints with the Ni/Cu/Ag metallization with longer sintering times removed the unwanted delamination failure mode and only left the preferred cohesive failure mode; moreover, the shear strength improved significantly, with values reaching 130 MPa. Furthermore, a new failure mode appears in the sintered Ag joint of the Ni/Cu/Ag stack, implying that the Al/Ni metallization weakness there is less of a limiting factor. This proves that our new metallization stack resolves present delamination issues in Ag sintered joints with Al heatsinks and DBA substrates and thereby supports exploiting the full potential of sintered Ag joints.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"203-211"},"PeriodicalIF":2.5,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Gamma Radiation on Static DC, Reliability, and RF Performance of Submicron GaN-on-Si RF MIS-HEMTs With In Situ SiN","authors":"Anant Johari;Chin-Ya Su;Der-Sheng Chao;Ankur Gupta;Rajendra Singh;Tian-Li Wu","doi":"10.1109/TDMR.2025.3573183","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3573183","url":null,"abstract":"This work demonstrates the synergistic effects of 100 kGy gamma irradiation on the electrical and reliability performance of submicron GaN-on-Si RF MIS-HEMTs with in situ SiN. The results reveal a significant reduction in contact and sheet resistance attributed to annealing effects and defect restructuring, as characterized by TLM measurements. These structural changes contribute to improvements in drain current and transconductance while maintaining a stable threshold voltage, as evidenced by input and output characteristics. Furthermore, the reliability characteristics, as measured by gate-lag/drain-lag measurements, confirm a reduction in trapping sites within the gate and gate-drain access regions, leading to improved ON-resistance stability post-gamma irradiation. A decrease in off-state leakage current and improved degradation voltage further supports the reduction of native defects, as confirmed by the gate and drain step stress measurements. The study also analyzes the RF performance using S-parameters and load-pull measurements, demonstrating improvements in small and large signal RF parameters driven by increased drain current and reduced trapped carriers. Collectively, these improvements in <inline-formula> <tex-math>$0.3~mu $ </tex-math></inline-formula>m gate-length GaN-on-Si RF MIS-HEMTs post-irradiation enable the design and fabrication of GaN MIS-HEMTs using the <inline-formula> <tex-math>$0.25~mu $ </tex-math></inline-formula>m industry semiconductor process, making them highly suitable for radiation-prone environments and space applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"465-472"},"PeriodicalIF":2.3,"publicationDate":"2025-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145043859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monitoring Metallized Film Capacitor Health: A Method for Estimating Capacitance Amid Short-Term Failures Due to Self-Healing","authors":"Yushuang He;Feipeng Wang;Hongming Yang;Archie James Johnston;Xiao Zhang;Jian Li","doi":"10.1109/TDMR.2025.3572512","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3572512","url":null,"abstract":"Metallized film capacitors (MFCs) are valued for their ability to withstand high-electric-fields, yet they face short-term failure risks when subjected to overvoltage-induced self-healing (SH). This paper presents a monitoring method designed to address the challenges posed by multiple instances of SH in pulsed power applications. Traditional capacitance estimation using sampled current during SH is hindered by the significant arc current. To address this, the study explores the dynamic interplay between sampling current, arc current, and MFC current throughout the SH process. The introduction of Kalman filtering effectively mitigates the impact of noise signals on capacitance monitoring during the short-term cumulative discharge process of SH. Experimental and simulation results attest to the efficiency of the proposed approach, demonstrating an estimation error of less than 1%. Furthermore, a thorough structural analysis of MFCs demonstrates that the proposed method can effectively identify the transition from isolated, safe SH behavior to clustered, disruptive SH events, thereby enabling timely intervention to prevent severe damage.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"638-648"},"PeriodicalIF":2.3,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single-Event Effects Induced by Monoenergetic Fast Neutrons in Silicon Power UMOSFETs","authors":"Saulo G. Alberton;Alexis C. Vilas-Bôas;Marcilei A. Guazzelli;Vitor A. P. Aguiar;Matheus S. Pereira;Nemitala Added;Claudio A. Federico;Tássio C. Cavalcante;Evaldo C. F. Pereira;Rafael G. Vaz;Odair L. Gonçalez;Jeffery Wyss;Alessandro Paccagnella;Nilberto H. Medina","doi":"10.1109/TDMR.2025.3572829","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3572829","url":null,"abstract":"The trench gate or U-groove MOSFET (UMOSFET) has become widely adopted as a semiconductor device globally, gradually replacing the traditional vertical double-diffused MOSFET (DMOSFET) in many applications. Evaluating the reliability of UMOSFETs regarding neutron-induced radiation effects is crucial for understanding their response to ubiquitous atmospheric neutrons. This study presents comparative experimental and computational results of Single-Event Effects induced by monoenergetic fast neutrons in UMOS and DMOS power transistors. Experiments demonstrate that UMOSFETs exhibit premature particle-induced avalanche multiplication effects compared to similarly rated DMOSFETs, which may favor destructive radiation effects, such as Single-Event Burnout, when operating in the terrestrial radiation environment.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"492-500"},"PeriodicalIF":2.3,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predictive Method of Charge Storage Memory Degradation on a Dedicated 4kb Test Vehicle","authors":"S. Perrin;K. Alkema;V. Della Marca;T. Kempf;O. Paulet;M. Arteaga;M. Akbal;B. Arrazat;J. Metz;J. M. Moragues;A. Regnier;M. Bocquet;J. M. Portal","doi":"10.1109/TDMR.2025.3572856","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3572856","url":null,"abstract":"This study investigates the variability in HCI (Hot Carrier Injection) degradation within a 4 kb charge storage memory array, manufactured on a dedicated wafer split process. A standard set of experiments is conducted to extract electrical features of the cells before and after stress. A statistical analysis method, based on the Principal Component Analysis (PCA) approach, is introduced to enhance the comprehension of the cell degradation prior to reliability testing. Additionally, a graphical model is developed to identify extrinsic cells in the memory array prior to stress, as well as to assess the overall technology yield. Finally, others classifier models are explored aiming to improve extrinsic cells detection before running the reliability test.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"371-378"},"PeriodicalIF":2.3,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Open Model Interface Assisted NBTI-Aware Design With Dual-Vth Logic Synthesis Strategy for Reliability Improvement","authors":"Wangyong Chen;Ling Xiong;Mingyue Zheng;Songxuan He;Linlin Cai","doi":"10.1109/TDMR.2025.3572299","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3572299","url":null,"abstract":"As CMOS technology scales down into the nanometer regime, the NBTI effect becomes a major issue for circuit reliability. This paper proposes an NBTI-aware design method with dual-Vth logic synthesis strategy for reliability improvement. NBTI awareness is innovatively incorporated into EDA toolchains based on NBTI-aware standard cell library and Open Model Interface (OMI), which considers aging difference among transistors instead of constant worst-case degradation. Furthermore, the circuit timing for post-aging delay is optimized by realizing the dual-Vth synthesis. The results show that in the original design without the optimal design strategy, the NBTI effect leads to obvious timing degradation. In contrast, when using the proposed OMI assisted design approach, timing degradation caused by NBTI can be suppressed effectively, allowing the circuit to continue operating normally even after aging.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"528-534"},"PeriodicalIF":2.3,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}