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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-06 DOI: 10.1109/TDMR.2024.3445849

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Correction to “Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130 nm to 28 nm Nodes and Beyond” 对 "针对 130 纳米至 28 纳米节点及更高节点超大规模器件的离态 TDDB 下通用介质击穿建模 "的更正

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-06 DOI: 10.1109/TDMR.2024.3429780

Tidjani Garba-Seybou;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho;Alain Bravaix

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Bridging the Data Gap in Photovoltaics with Synthetic Data Generation 通过合成数据生成弥补光伏领域的数据差距

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-06 DOI: 10.1109/TDMR.2024.3424970

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IEEE Transactions on Device and Materials Reliability Information for Authors IEEE 《器件与材料可靠性》期刊为作者提供的信息

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-06 DOI: 10.1109/TDMR.2024.3445848

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IEEE Transactions on Device and Materials Reliability Publication Information IEEE 器件与材料可靠性期刊》出版信息

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IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-06 DOI: 10.1109/TDMR.2024.3445828

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Dimension Influence on the Interface Fatigue Characteristics of Three-Dimensional TSV Array: A Fully Coupled Thermal-Electrical-Structural Analysis 尺寸对三维 TSV 阵列界面疲劳特性的影响：热、电、结构全耦合分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-03 DOI: 10.1109/TDMR.2024.3453923

Kaihong Hou;Zhengwei Fan;Shufeng Zhang;Yashun Wang;Xun Chen

{"title":"Dimension Influence on the Interface Fatigue Characteristics of Three-Dimensional TSV Array: A Fully Coupled Thermal-Electrical-Structural Analysis","authors":"Kaihong Hou;Zhengwei Fan;Shufeng Zhang;Yashun Wang;Xun Chen","doi":"10.1109/TDMR.2024.3453923","DOIUrl":"10.1109/TDMR.2024.3453923","url":null,"abstract":"As the interconnected structure of 3D chip, through-silicon via undertakes the key functions in energy transmission, mechanical support and signal transmission of 3D chip. With the increasing of TSV interconnection density, the reliability of TSV is becoming increasingly prominent, and the slight variation of TSV dimension may exert severe impact on the fatigue life of the TSV array. In this study, a typical double-layer TSV interconnected 3D array is built to carried out the multi-interface fatigue analysis under thermoelectric structure coupling field, the influence of different dimension of the TSV interconnected array on the fatigue life of various interface and whole thermoelectric circuit are deeply investigated. Results shows that: 1) relatively small or large diameter of TSV-Cu or Bump can effectively improve the fatigue life of Bump-RDL interface. 2) The fatigue life of the top interface between TSV-Cu and SiO2 layer is slightly higher than that of the bottom interface. 3) The optimal dimension combination of TSV interconnected array is highly related with external working environment and own working state. Under the condition of this study, the dimension corresponding to Case 0 (TSV-Cu diameter: \u0000<inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>\u0000m, Bump diameter: \u0000<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>\u0000m, Pitch: \u0000<inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>\u0000m, SiO2 layer thickness: \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000m) is the optimal solution. 4) TSV-Cu diameter and SiO2 thickness have the greatest influence on the fatigue life of TSV array. Relevant results can provide valuable references for locating the weak points of the TSV interconnected array and the subsequent optimization design.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"571-583"},"PeriodicalIF":2.5,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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An Efficient Dynamic Threshold Voltage Detection Scheme for Improving 3-D NAND Flash Reliability 提高 3D NAND 闪存可靠性的高效动态阈值电压检测方案

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-02 DOI: 10.1109/TDMR.2024.3453329

Linxin Yin;Yingzhao Li;Xiaoyi Zhang;Xiongfei Zhai;Guojun Han

{"title":"An Efficient Dynamic Threshold Voltage Detection Scheme for Improving 3-D NAND Flash Reliability","authors":"Linxin Yin;Yingzhao Li;Xiaoyi Zhang;Xiongfei Zhai;Guojun Han","doi":"10.1109/TDMR.2024.3453329","DOIUrl":"10.1109/TDMR.2024.3453329","url":null,"abstract":"With high storage density and large capacity, three-dimensional (3D) NAND flash utilizing multi-level storage technology has become the mainstream storage medium. Furthermore, by storing multiple bits in each flash cell, 3D NAND flash memory can achieve much larger storage capacity. However, the threshold voltage distribution in 3D NAND flash memory tends to shift after repeated program/erase and long retention time, leading to more detection error when adopting conventional fixed read reference voltage (RRV). To address this issue, in this work we investigate error characteristics of 3D floating-gate (FG) and charge-trap (CT) NAND flash memory, including the reliability variations of different layers and pages, and threshold voltage shifting. We propose an efficient dynamic threshold voltage detection (EDTVD) scheme by exploiting the error characteristics and the features of the data writing process of NAND flash to optimize RRV. Based on the Nanocycler test platform, the test results show that our proposed scheme can significantly reduce raw bit error rates (RBER) during reading processes and the step count is relatively low. The RBER of the EDTVD scheme is almost equal to the optimal read scheme, and the number of step count is close to 3 fixed-step read scheme.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"529-543"},"PeriodicalIF":2.5,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Unveiling the Degradation Mechanism of Polymer-Based Thermal Interface Materials Under Thermo-Oxidative Condition 揭示聚合物热界面材料在热氧化条件下的降解机理

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-08-15 DOI: 10.1109/TDMR.2024.3442781

Yongdong Wu;Bin He;Jingyuan Fang;Yuqi Hu;Xiaoliang Zeng;Linlin Ren;Rong Sun

{"title":"Unveiling the Degradation Mechanism of Polymer-Based Thermal Interface Materials Under Thermo-Oxidative Condition","authors":"Yongdong Wu;Bin He;Jingyuan Fang;Yuqi Hu;Xiaoliang Zeng;Linlin Ren;Rong Sun","doi":"10.1109/TDMR.2024.3442781","DOIUrl":"10.1109/TDMR.2024.3442781","url":null,"abstract":"With the growing power density and miniaturization of electronic devices, their thermal management and reliability are becoming more and more important. Polymer-based thermal interface materials, which are used to fill the gap between chip and heat sink, play an important role for the heat dissipation, but their reliability is rarely studied in academia, especially under thermo-oxidative condition. Here, a polymer-based thermal interface material, highly filled thermal conductive gel, is used as a model to study the degradation mechanism under thermo-oxidative condition. The results show that aging mainly deteriorates the mechanical performance instead of its intrinsic thermal conductivity. The elongation at break of aged sample is reduced and the corresponding modulus is increased as a function of aging time. Relaxation spectra indicate that the relaxation time of aged sample increases. The longer relaxation time of aged sample is attributed to the chain scission and oxidation of alky chain at interface and the depolymerization of polydimethylsiloxane chain, resulting in a more crosslinked polymer network. Thus, both interfacial aging and depolymerization of polymers contribute to the slowdown of polymer chain dynamics and degradation of mechanical properties. This work provides an insight into the degradation mechanism of thermal interface materials and guides the development of high-reliability thermal interface materials.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"514-521"},"PeriodicalIF":2.5,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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All-Regions Damage Extraction Method for SiC IGBTs Based on C-V Curves 基于 C-V 曲线的 SiC IGBT 全区域损伤提取方法

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-08-13 DOI: 10.1109/TDMR.2024.3443107

Junhou Cao;Chenlu Wang;Lei Huang;Tuanzhuang Wu;Hao Fu;Zhaoxiang Wei;Zhaoxu Song;Shaohong Li;Jiaxing Wei;Siyang Liu;Weifeng Sun

{"title":"All-Regions Damage Extraction Method for SiC IGBTs Based on C-V Curves","authors":"Junhou Cao;Chenlu Wang;Lei Huang;Tuanzhuang Wu;Hao Fu;Zhaoxiang Wei;Zhaoxu Song;Shaohong Li;Jiaxing Wei;Siyang Liu;Weifeng Sun","doi":"10.1109/TDMR.2024.3443107","DOIUrl":"10.1109/TDMR.2024.3443107","url":null,"abstract":"SiC IGBTs take the advantages of high breakdown voltage and high conduction current, being a new type of power device with great application prospects in power transmission fields. However, foreseeable stress conditions such as gate stress, irradiation, and bipolar conduction may cause damage to the gate oxide and the epitaxial layer of SiC IGBTs, leading to degradation. Analysis of the device capacitance components shows that the damages in the gate oxide and the epitaxial layer results in variations in the gate capacitance and the substrate junction capacitance before and after enduring a stress. Therefore, the all-regions damage extraction method for SiC IGBT based on C-V curves is proposed for the first time. This method divides the \u0000<inline-formula> <tex-math>${C}_{text {G}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000 curve of SiC IGBT into six parts, whose shifts can reflect the damages in the gate oxide damage and epitaxial layer, respectively. Furthermore, the polarity and the degree of the damages can be extracted based on the direction and magnitude of the drift in the \u0000<inline-formula> <tex-math>${C}_{text {G}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000 curve. Moreover, by analyzing the drift in the \u0000<inline-formula> <tex-math>${C}_{text {GC}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {CE}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$text {1/}{C}_{text {GC}}^{{2}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {CE}}$ </tex-math></inline-formula>\u0000 curves before and after stress, the more accurate extraction of the density and localization of defect introduced in epitaxial layer can be achieved.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"522-528"},"PeriodicalIF":2.5,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Exploring Non-TAP Interfaces for Efficient and Secure Access to IJTAG Network 探索高效安全访问 IJTAG 网络的非 TAP 接口

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-08-07 DOI: 10.1109/TDMR.2024.3440059

Anjum Riaz;Gaurav Kumar;Lavi Tyagi;Yamuna Prasad;Satyadev Ahlawat

{"title":"Exploring Non-TAP Interfaces for Efficient and Secure Access to IJTAG Network","authors":"Anjum Riaz;Gaurav Kumar;Lavi Tyagi;Yamuna Prasad;Satyadev Ahlawat","doi":"10.1109/TDMR.2024.3440059","DOIUrl":"10.1109/TDMR.2024.3440059","url":null,"abstract":"The IEEE Std. 1687 (IJTAG) enables efficient access to on-chip instruments through the Test Access Port (TAP) controller of IEEE Std. 1149.1 (JTAG). However, practical constraints such as physical size, manufacturing intricacies, and cost considerations often pose challenges in allocating test IO pins exclusively for TAP usage, especially in resource constraint ICs. To circumvent these limitations, the IEEE Std. P1687.1 explores alternative means of utilizing functional ports, such as Inter-integrated Circuit (I2C), Universal Asynchronous Receiver-Transmitter (UART), and Serial Peripheral Interface (SPI), as non-TAP device interfaces. Recently, a protocol that utilizes UART as a device interface to access on-chip instruments has been proposed. However, this protocol suffers from excessive access time and data overhead and lacks security considerations. To address these issues, this paper presents a low-cost, secure access protocol. The proposed protocol is able to reduce the access time and data overhead by a maximum of 45.51% and 69.66%, respectively, and it incurs a minimal area overhead. Additionally, the protocol integrates robust security measures based on data encryption, thwarting both local and remote intruders from stealing useful information over the IJTAG network.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"76-84"},"PeriodicalIF":2.5,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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