IEEE Transactions on Device and Materials Reliability最新文献

{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2024.3516718","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3516718","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"C3-C3"},"PeriodicalIF":2.5,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812196","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Blank Page","authors":"","doi":"10.1109/TDMR.2024.3516719","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3516719","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"C4-C4"},"PeriodicalIF":2.5,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812197","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial on EOS","authors":"Ming-Dou Ker","doi":"10.1109/TDMR.2024.3507412","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3507412","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"471-471"},"PeriodicalIF":2.5,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812359","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Call for Nominations for Editor-in-Chief","authors":"","doi":"10.1109/TDMR.2024.3513737","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3513737","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"663-663"},"PeriodicalIF":2.5,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812200","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications","authors":"Gowthami Ryali;Bala Subrahmanyam Pitchuka;Venkata Ramakrishna Kotha;Sresta Valasa;Sunitha Bhukya;Praveen Kumar Mudidhe;Shubham Tayal;Bheemudu Vadthya;Hitesh Borkar;Narendar Vadthiya","doi":"10.1109/TDMR.2024.3516084","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3516084","url":null,"abstract":"In the recent times, the Forksheet (FS) FET has evolved as a potential candidature for next generation applications due the seamless integration of nFET and pFET with minimal n-p spacing. However, one of the serious concerns that bothers the reliability of devices is the presence of interface traps. Therefore, in this manuscript, for the first time, we aim to analyse the presence of acceptor and donor interface trap charges (ITCs) in sub - 3nm technology node for the Junctionless (JL) FSFET with well calibrated TCAD setup for digital, analog/RF, and circuit applications. Results demonstrated that the presence of acceptor ITCs in nFET and donor ITCs in pFET in the JL-FSFET device improves the overall digital performance of the device with switching ratio <inline-formula> <tex-math>$sim 10{^{{10}}}$ </tex-math></inline-formula> when compared to no trap scenario. At lower VGS, the presence of ITCs significantly impacted the analog/RF performance whereas increasing the VGS after a certain point overpowered the trap effects producing invariant changes in analog/RF performance indicating that the designed JL-FSFET is reliable and robust. Further, increasing the trap concentration from <inline-formula> <tex-math>$2times 10{^{{12}}}~{mathrm { cm}}^{-2}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$8times 10{^{{12}}}~{mathrm { cm}}^{-2}$ </tex-math></inline-formula> reduced the leakage currents in four orders and improved the switching ratio by <inline-formula> <tex-math>$sim 10{^{{12}}}$ </tex-math></inline-formula> especially with the presence of acceptor ITCs in nFET and donor ITCs in pFET. Moreover, increasing the trap concentration at higher VGS, produced equal analog/RF performance with that of absence of traps making the device more reliable even with higher concentrations. The CMOS inverter layout for the JL-FSFET is designed with the presence and absence of ITCs and found that the ITCs based inverter produces near equal gain to that of no traps. Overall, this research paves a way towards the reliable performance of JL-FSFET in the presence of ITCs to be adopted into next generation digital, analog/RF IC applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"119-127"},"PeriodicalIF":2.5,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cohesive Zone Parameters Extraction for Sintered Nano Ag/Al Joints With the Different Surface Finish Layers Under High Temperature Aging","authors":"Libo Zhao;Yanwei Dai;Fei Qin","doi":"10.1109/TDMR.2024.3513318","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3513318","url":null,"abstract":"Because of its outstanding advantages, sintered nano silver is considered the most promising interconnect material in power module packaging such as silicon carbide (SiC). In view of the wettability of the interface between sintered nano silver and metal substrate, the influence of the metallization layer, which is adopted to improve the wettability of the interface between sintered nanosilver and metal substrate, on the interface bonding strength has also become a research focus. In this paper, a cohesive zone model (CZM), which can describe the failure damage and shear fracture process, is used to predict the bonding strength of “sandwich” structures with different metallization layers based on the die shear test. Considering the effect of high temperature aging, the mechanism of different substrate metallization and high temperature aging conditions on the shear strength of sintered silver interconnect layer was presented. Based on the fracture surface morphology of sintered silver adhesive joint, the mechanism of bonding strength of samples with different metallization layers changes with high temperature aging is verified. In addition, the CZM model and related parameters proposed in this paper can be directly used to evaluate the reliability of sintered Ag-Al interface in power device applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"101-109"},"PeriodicalIF":2.5,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault Modeling and Test Algorithm Development Framework for Gate-All-Around SRAMs","authors":"Artur Ghukasyan;Karen Amirkhanyan;Grigor Tshagharyan;Gurgen Harutyunyan;Yervant Zorian","doi":"10.1109/TDMR.2024.3513549","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3513549","url":null,"abstract":"With the transition from planar to three-dimensional transistor architectures, many new factors have entered the scene, highlighting the need for thorough investigation of ever-shrinking technology nodes, as well as the development of advanced methodologies capable of addressing the challenges of testing modern complex memory systems. This paper examines the challenges associated with Gate-All-Around emerging technology paradigm and proposes a conceptual framework aimed at comprehensively investigating the universe of realistic defects, accurately modeling the resulting faulty behavior, and ultimately developing effective test solutions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"37-44"},"PeriodicalIF":2.5,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Asymmetric Trench SiC MOSFET With Integrated Three Channels for Improved Performance and Reliability","authors":"Weizhong Chen;Yangqi Zhou;Yufan Xiao;Hongsheng Zhang;Yi Huang;Zhengsheng Han","doi":"10.1109/TDMR.2024.3510782","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3510782","url":null,"abstract":"A novel Asymmetric Trench SiC MOSFET (ATMOS) with Integrated Three Channels (ITC) is presented, which improves the performance and reliability significantly. The ITC includes the reverse conduction channel (Ch3) and double forward conduction channels (Ch1 and Ch2). The Ch3 is constituted by the Self-Biased MOSFET (SBM), forming a low barrier due to the drain-induced barrier lowering effect, which results in a lower turn on voltage compared with the p-i-n body diode. On the other hand, the Ch1 and Ch2 are constituted by the side trench MOSFET and additional bottom planar MOSFET, respectively. It shortens the width of the JFET region, and a lower gate oxide electric field is achieved. The reverse blocking leakage current (IBL) caused by the drain-induced barrier lowering is suppressed. Moreover, the bottom planar MOSFET reduces the gate-drain charge (QGD) and switching losses due to the reduced coupling area between the Gate and Drain. Finally, The Ch1 and Ch2 provide double electron current paths during forward concoction, which reduces the specific on-resistance (Ron,sp) of the device remarkably. The simulation results show that the proposed ITC-ATMOS achieves a reduction <inline-formula> <tex-math>${mathrm { V}}_{mathrm { cut-in}}$ </tex-math></inline-formula> of the body diode from 2.8V to 2.0V at 50A. The peak electric field <inline-formula> <tex-math>${mathrm { E}}_{mathrm { max}}$ </tex-math></inline-formula> is reduced to 1.27MV, and the leakage current(IBL) caused by the integrated SBM (I<inline-formula> <tex-math>${_{text {BL}}} {=} 10{^{-}7 }$ </tex-math></inline-formula> A) is much smaller than integrated Schottky Barrier Diodes (SBD) (I<inline-formula> <tex-math>${_{text {BL}}} {=} 10{^{-}5 }$ </tex-math></inline-formula> A) for blocking characteristics at high-temperature, thus long-term reliability is greatly enhanced. Moreover, a decrease in <inline-formula> <tex-math>${mathrm { R}}_{mathrm { on,sp}}$ </tex-math></inline-formula> of 28.57%, and reductions in <inline-formula> <tex-math>${mathrm { Q}}_{mathrm { GD}}$ </tex-math></inline-formula> and switching losses by 20.60% and 41.4% are achieved when compared with the Conventional ATMOS, respectively.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"95-100"},"PeriodicalIF":2.5,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanism and Quantitative Modeling of the SRAM Soft Error Induced by Space Electrostatic Discharge","authors":"R.-J. Yuan;Rui Chen;J.-W. Han;Y.-N. Liang;Z.-Y. Wang;H.-L. Yu","doi":"10.1109/TDMR.2024.3510716","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3510716","url":null,"abstract":"This study investigates the characteristics, sensitive regions, failure mechanism, and quantitative model of the SRAM soft errors caused by spacecraft charging-induced electrostatic discharge (SESD) in HSPICE simulations. The results revealed that ‘1-0’ bit upset was one of the main characteristics of the soft errors caused by the SESD. The SESD-sensitive regions were located at the sense amplifier (AMP) and the 6T bit-cell array, with the SESD injecting at the power supply nodes. The main failure mechanisms are the reduction in the voltage difference between the two output nodes of the AMP and the recoverable breakdown in the P-channel metal oxide semiconductor (PMOS) of the 6T-cell, which is induced by the SESD transients. The quantization calculation model of the soft error induced by SESD for SRAM was established via MATLAB according to its failure mechanism, which bridged the characteristics of the SESD transient with the SRAM soft error to quickly evaluate the SESD errors. In addition, the quantization model was preliminarily verified via SESD experiments.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"110-118"},"PeriodicalIF":2.5,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Gate-Level SER Estimation Tool With Event-Driven Dynamic Timing and SET Height Consideration","authors":"Georgios-Ioannis Paliaroutis;Pelopidas Tsoumanis;Dimitrios Garyfallou;Anastasis Vagenas;Nestor Evmorfopoulos;Georgios Stamoulis","doi":"10.1109/TDMR.2024.3508696","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3508696","url":null,"abstract":"Radiation-induced soft errors in Integrated Circuits (ICs) have always been a matter of great reliability concern. However, the ongoing shrinking of CMOS technology nodes, which results in high frequency, low power, and small area exacerbates the problem. Thus, accurate evaluation of the ICs’ vulnerability to such errors has become crucial, especially when a radiation-hardening process is developed. In this article, we present a gate-level Soft Error Rate (SER) estimation framework based on an event-driven approach that models the generated Single Event Transients (SETs) as event pairs that propagate through the circuit. Dynamic Timing Analysis (DTA) is performed to estimate SET arrival times at Flip-Flop (FF) inputs and detect a soft error. Moreover, our approach approximates the glitch height and considers the noise immunity thresholds of gates to evaluate potential SET electrical masking. Additionally, our event-driven framework enables accurate propagation of Single Event Multiple Transients (SEMTs), which have become commonplace in combinational circuits. Experimental evaluation on ISCAS ’89 benchmarks indicates that the proposed event-driven height-aware approach exhibits 21.06% more accurate SER estimation on average, compared to conventional graph-based techniques, with respect to SPICE simulation. F1 scores further strengthen the previous result, demonstrating an average improvement of 11.86%. In terms of failures in time, experimental results show that the graph-based approach overestimates SER by an average of 8558 and up to 16485 errors compared to the proposed method. Finally, our approach is used to effectively identify the most sensitive gates that could potentially be hardened in a SER mitigation scenario.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"17-26"},"PeriodicalIF":2.5,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}