IEEE Transactions on Device and Materials Reliability最新文献_第4页

Early Radiation-Induced Soft-Error Assessment of Arm Cortex-M SoCs Through Fault Injection

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-18 DOI: 10.1109/TDMR.2024.3501193

Leonardo Gobatto;Fabio Benevenuti;Rodrigo Possamai Bastos;Nemitala Added;Saulo Alberton;Eduardo Macchione;Vitor Aguiar;Nilberto Medina;Fernanda Kastensmidt;Jose Rodrigo Azambuja

引用次数: 0

Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity 基于增强抗噪性的抗辐射Domino逻辑Schmitt触发电路

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-12 DOI: 10.1109/TDMR.2024.3496821

Aryan Kannaujiya;Shubham Singh;Ambika Prasad Shah;Daniele Rossi

{"title":"Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity","authors":"Aryan Kannaujiya;Shubham Singh;Ambika Prasad Shah;Daniele Rossi","doi":"10.1109/TDMR.2024.3496821","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3496821","url":null,"abstract":"This work presents enhanced hysteresis width for noise-immune radiation-hardened Schmitt trigger circuits. A dual-mode Domino-based Schmitt trigger (DST) circuit is employed for dual purposes owing to the inclusion of a control module that functions as both a domino logic and a Schmitt trigger circuit. For various ST circuits, key performance metrics including hysteresis width, power consumption, latency, process variation, and critical charge at sensitive nodes are determined. The findings demonstrate that, in comparison to other reference circuits, the DST has improved performance metrics. The proposed DST has \u0000<inline-formula> <tex-math>$3.89times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$1.58times $ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$1.03times $ </tex-math></inline-formula>\u0000 lower dynamic power, leakage power, and propagation delay, respectively in comparison to conventional ST. The hysteresis width of DST is \u0000<inline-formula> <tex-math>$1.32times $ </tex-math></inline-formula>\u0000 higher than conventional ST which makes it more practical for a noisy environment. All the simulation work has been handled by the Cadence virtuoso tool using UMC 40nm technology.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"602-609"},"PeriodicalIF":2.5,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Trap Location and Stress Degradation Analysis of GaN High Electron Mobility Transistors Based on the Transient Current Method 基于瞬态电流法的氮化镓高电子迁移率晶体管陷阱定位与应力退化分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-11 DOI: 10.1109/TDMR.2024.3495987

Qian Wen;Lixing Zhou;Xianwei Meng;Shiwei Feng;Yamin Zhang

{"title":"Trap Location and Stress Degradation Analysis of GaN High Electron Mobility Transistors Based on the Transient Current Method","authors":"Qian Wen;Lixing Zhou;Xianwei Meng;Shiwei Feng;Yamin Zhang","doi":"10.1109/TDMR.2024.3495987","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3495987","url":null,"abstract":"In this paper, the carrier trapping behavior and electrical characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) under different bias conditions are studied based on the transient current. By considering the transient drain current of HEMTs at different temperatures, three trapping mechanisms are identified: (1) charge trapping in the AlGaN barrier layer, in the gate-drain region near the two-dimensional electron gas (2DEG) channel; (2) charge trapping in the GaN layer, in the gate-drain region near the gate; and (3) charge trapping on the surface of the AlGaN layer, in the gate-drain region near the gate. The influences of the source-gate and drain-gate voltages on trapping behavior are analyzed to further elucidate the trap locations. The experimental results show that charge capture is mainly affected by the drain-gate voltage. High electric field stress affects the local structure order inside the device, thus affecting the charge escape rate. The threshold voltage shift is mainly affected by the surface trap of the AlGaN layer near the gate.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"624-630"},"PeriodicalIF":2.5,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform 总电离剂量对新兴垂直背栅CMOS平台DC/RF性能的影响

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-11-01 DOI: 10.1109/TDMR.2024.3488750

Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky

{"title":"Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform","authors":"Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky","doi":"10.1109/TDMR.2024.3488750","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3488750","url":null,"abstract":"As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"637-645"},"PeriodicalIF":2.5,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study on Electromagnetic Pulse Damage of 22nm FDSOI in Radiation Environment 22nm FDSOI在辐射环境中的电磁脉冲损伤研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-23 DOI: 10.1109/TDMR.2024.3485095

Chen Chong;Xing Li;Hongxia Liu;Wei Zhou;Menghao Huang

引用次数: 0

Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress 极高栅极电压应力下SiC mosfet栅氧化可靠性评估

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-18 DOI: 10.1109/TDMR.2024.3478220

Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang

引用次数: 0

Dependability and Protection of Transformer Models Against Soft Errors on Text Embeddings 变压器模型的可依赖性和保护，防止文本嵌入出现软错误

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-11 DOI: 10.1109/TDMR.2024.3478753

Zhen Gao;Shuang Liu;Pedro Reviriego;Shanshan Liu;Fabrizio Lombardi

{"title":"Dependability and Protection of Transformer Models Against Soft Errors on Text Embeddings","authors":"Zhen Gao;Shuang Liu;Pedro Reviriego;Shanshan Liu;Fabrizio Lombardi","doi":"10.1109/TDMR.2024.3478753","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3478753","url":null,"abstract":"Transformers have achieved remarkable success in diverse fields such as Natural Language Processing (NLP) and computer vision (CV). For pre-trained Transformer models involving text processing, embedding representations are important parameters, incurring a large volume of memory. Soft errors on embedding vectors can lead to incorrect inputs to Transformers, and if not corrected in time, accumulated errors may produce undesirable outcomes. This paper considers the dependability of text related Transformer models to accumulated errors on embedding parameters and takes three typical models in different applications as case studies: BERT based sentence emotion classification, T5 based text summarization, and CLIP based image classification. We first evaluate the dependability of the three models by injecting bit errors on embedding parameters; only errors on a few critical bits affect model performance. Based on this finding, we first propose an efficient selective protection for embedding parameters with small values, and then through scaling, we extend the scheme for models with large embedding parameters. Extensive simulation results show that the proposed protection scheme can effectively remove the impact of soft errors on task performance. In particular, the complexity overhead of the proposed scheme is negligible, and the additional memory overhead as encountered in the SEC scheme is avoided.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"54-65"},"PeriodicalIF":2.5,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of Thermal Expansion Behavior and Interface Evolution of TSV Under Thermal Cycle Loading Based on Crystal Plastic Finite Element Method 基于晶体塑性有限元法的TSV热循环载荷下热膨胀行为及界面演化分析

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-10 DOI: 10.1109/TDMR.2024.3478183

Kaihong Hou;Zhengwei Fan;Xun Chen;Shufeng Zhang;Yashun Wang;Yu Jiang

引用次数: 0

Investigating the Arc-Shaped Kink Drain Voltage of Drain Current With Capacitance-Voltage Measurement Method in GaN HEMTs 用电容电压测量法研究GaN hemt中漏极电流的弧形结漏极电压

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-30 DOI: 10.1109/TDMR.2024.3467344

Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang

{"title":"Investigating the Arc-Shaped Kink Drain Voltage of Drain Current With Capacitance-Voltage Measurement Method in GaN HEMTs","authors":"Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang","doi":"10.1109/TDMR.2024.3467344","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467344","url":null,"abstract":"In this study, the measure-stress-measure (MSM) technique under the arc-shaped kink drain voltage (VD,kink) conditions is applied to investigate the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 in GaN high electron mobility transistors (HEMTs). Forward and reverse transfer curves indicate that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 would change with gate voltages increasing. However, no previous study has investigated the exact location of traps that would dominate the loci of VD,kink. The results suggest that the trend of on-state current (Ion) degradation is caused by threshold voltage (Vt) shift. Hence, it can be determined that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 is related to the degree of impact ionization, which is dominant by the holes generation in the buffer. In addition, the capacitance-voltage (C-V) measurements reveal that holes generated through impact ionization at the gate edge are responsible for the shift in VD,kink. This physical mechanism is further supported by temperature-dependent analysis. Finally, the results offer a novel C-V measurement to characterize and model the physical mechanisms of the kink effect, which is governed by hot carrier degradation in GaN HEMTs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"544-548"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Switching Characteristics Degradation of GaN HEMT Under Power Cycling Aging 功率循环老化下GaN HEMT开关特性退化研究

IF 2.5 3区工程技术

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-09-30 DOI: 10.1109/TDMR.2024.3468013

Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han

{"title":"Investigation of Switching Characteristics Degradation of GaN HEMT Under Power Cycling Aging","authors":"Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han","doi":"10.1109/TDMR.2024.3468013","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468013","url":null,"abstract":"GaN HEMT devices have wide application prospects because of their high electron mobility and excellent electrical characteristics. However, due to the lack of reliability analysis of the switching characteristics, GaN HEMT devices are unable to realize their maximum potential in practical applications. In this paper, GaN HEMT devices are aged based on power cycling. The switching degradation behavior of GaN HEMT devices after aging is characterized by double pulse test. The test results show that the switching delay increases, the Miller platform lengthens, and the opening ringing decreases after power cycle aging. In order to explore the degradation mechanism, the effects of parasitic capacitance on the switching characteristics are characterized by double pulse test of parallel capacitors. Based on the analysis of the parasitic capacitance model, the degradation trend of each parasitic capacitance caused by trap after aging is deduced and verified by experiment. The results show that the trap increase of AlGaN layer caused by inverse piezoelectric effect and hot-electron effect is the main reason for the change of parasitic capacitance after aging, while the on-state and off-state capacitance of GaN HEMT devices have completely different composition mechanism and change trends, which lead to different trends and degrees of degradation of each switching characteristic. This can provide a valuable reference for the reliability of GaN HEMT devices in long-term applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"610-617"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0