IEEE Transactions on Device and Materials Reliability最新文献

{"title":"An Efficient Dynamic Threshold Voltage Detection Scheme for Improving 3-D NAND Flash Reliability","authors":"Linxin Yin;Yingzhao Li;Xiaoyi Zhang;Xiongfei Zhai;Guojun Han","doi":"10.1109/TDMR.2024.3453329","DOIUrl":"10.1109/TDMR.2024.3453329","url":null,"abstract":"With high storage density and large capacity, three-dimensional (3D) NAND flash utilizing multi-level storage technology has become the mainstream storage medium. Furthermore, by storing multiple bits in each flash cell, 3D NAND flash memory can achieve much larger storage capacity. However, the threshold voltage distribution in 3D NAND flash memory tends to shift after repeated program/erase and long retention time, leading to more detection error when adopting conventional fixed read reference voltage (RRV). To address this issue, in this work we investigate error characteristics of 3D floating-gate (FG) and charge-trap (CT) NAND flash memory, including the reliability variations of different layers and pages, and threshold voltage shifting. We propose an efficient dynamic threshold voltage detection (EDTVD) scheme by exploiting the error characteristics and the features of the data writing process of NAND flash to optimize RRV. Based on the Nanocycler test platform, the test results show that our proposed scheme can significantly reduce raw bit error rates (RBER) during reading processes and the step count is relatively low. The RBER of the EDTVD scheme is almost equal to the optimal read scheme, and the number of step count is close to 3 fixed-step read scheme.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"529-543"},"PeriodicalIF":2.5,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unveiling the Degradation Mechanism of Polymer-Based Thermal Interface Materials Under Thermo-Oxidative Condition","authors":"Yongdong Wu;Bin He;Jingyuan Fang;Yuqi Hu;Xiaoliang Zeng;Linlin Ren;Rong Sun","doi":"10.1109/TDMR.2024.3442781","DOIUrl":"10.1109/TDMR.2024.3442781","url":null,"abstract":"With the growing power density and miniaturization of electronic devices, their thermal management and reliability are becoming more and more important. Polymer-based thermal interface materials, which are used to fill the gap between chip and heat sink, play an important role for the heat dissipation, but their reliability is rarely studied in academia, especially under thermo-oxidative condition. Here, a polymer-based thermal interface material, highly filled thermal conductive gel, is used as a model to study the degradation mechanism under thermo-oxidative condition. The results show that aging mainly deteriorates the mechanical performance instead of its intrinsic thermal conductivity. The elongation at break of aged sample is reduced and the corresponding modulus is increased as a function of aging time. Relaxation spectra indicate that the relaxation time of aged sample increases. The longer relaxation time of aged sample is attributed to the chain scission and oxidation of alky chain at interface and the depolymerization of polydimethylsiloxane chain, resulting in a more crosslinked polymer network. Thus, both interfacial aging and depolymerization of polymers contribute to the slowdown of polymer chain dynamics and degradation of mechanical properties. This work provides an insight into the degradation mechanism of thermal interface materials and guides the development of high-reliability thermal interface materials.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"514-521"},"PeriodicalIF":2.5,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"All-Regions Damage Extraction Method for SiC IGBTs Based on C-V Curves","authors":"Junhou Cao;Chenlu Wang;Lei Huang;Tuanzhuang Wu;Hao Fu;Zhaoxiang Wei;Zhaoxu Song;Shaohong Li;Jiaxing Wei;Siyang Liu;Weifeng Sun","doi":"10.1109/TDMR.2024.3443107","DOIUrl":"10.1109/TDMR.2024.3443107","url":null,"abstract":"SiC IGBTs take the advantages of high breakdown voltage and high conduction current, being a new type of power device with great application prospects in power transmission fields. However, foreseeable stress conditions such as gate stress, irradiation, and bipolar conduction may cause damage to the gate oxide and the epitaxial layer of SiC IGBTs, leading to degradation. Analysis of the device capacitance components shows that the damages in the gate oxide and the epitaxial layer results in variations in the gate capacitance and the substrate junction capacitance before and after enduring a stress. Therefore, the all-regions damage extraction method for SiC IGBT based on C-V curves is proposed for the first time. This method divides the \u0000<inline-formula> <tex-math>${C}_{text {G}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000 curve of SiC IGBT into six parts, whose shifts can reflect the damages in the gate oxide damage and epitaxial layer, respectively. Furthermore, the polarity and the degree of the damages can be extracted based on the direction and magnitude of the drift in the \u0000<inline-formula> <tex-math>${C}_{text {G}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {G}}$ </tex-math></inline-formula>\u0000 curve. Moreover, by analyzing the drift in the \u0000<inline-formula> <tex-math>${C}_{text {GC}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {CE}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$text {1/}{C}_{text {GC}}^{{2}}$ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>${V}_{text {CE}}$ </tex-math></inline-formula>\u0000 curves before and after stress, the more accurate extraction of the density and localization of defect introduced in epitaxial layer can be achieved.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"522-528"},"PeriodicalIF":2.5,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring Non-TAP Interfaces for Efficient and Secure Access to IJTAG Network","authors":"Anjum Riaz, Gaurav Kumar, Lavi Tyagi, Yamuna Prasad, Satyadev Ahlawat","doi":"10.1109/tdmr.2024.3440059","DOIUrl":"https://doi.org/10.1109/tdmr.2024.3440059","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"131 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Hot Carrier Degradation on Total Ionizing Dose in Bulk I/O-FinFETs","authors":"Ruxue Yao;Hongliang Lu;Yuming Zhang;Yutao Zhang;Jing Qiao;Jing Sun;Mingzhu Xun;Gang Yu","doi":"10.1109/TDMR.2024.3431633","DOIUrl":"10.1109/TDMR.2024.3431633","url":null,"abstract":"Electronic components operating in aerospace environments face a variety of reliability issues. The total ionization dose (TID) degradation mechanism of bulk I/O-FinFETs and the influence of hot carrier degradation (HCD) on TID irradiation are investigated in this paper. Devices under ON/TG/OFF bias conditions were irradiated to 2 Mrad (Si). The nFinFETs show degradation of threshold voltage, subthreshold swing and off-state leakage current. An increase in peak transconductance and on-state current was also observed in the nFinFETs. The TID response of nFinFETs is dominated by positively trapped charges in the gate oxide and shallow trench isolation (STI). For pFinFETs, radiation-induced hole-trapped charges leads to an increase in the threshold voltage and a decrease in the drive current. The worst degradation is observed when a high electric field is applied to the gate during irradiation. Post-stress irradiation results show that the HCD and TID degradation trends of the nFinFETs are opposite and have a mutual canceling effect, while the degradation trends of the pFinFETs are consistent and jointly deteriorate the device performance. Compared to the un-stressed devices, the TID damage of the pre-stressed devices is more drastic, especially for the nFinFETs. The stress-induced interface trapped charges increase the electric field in the gate oxide during subsequent irradiation, which causes more radiation-induced hole-trapped charges and exacerbate TID degradation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"456-462"},"PeriodicalIF":2.5,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141868453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Layout Parameter Mismatches on Short Circuit Reliability of Parallel-Connected Planar, Trench, and Double-Trench SiC MOSFETs","authors":"Renze Yu;Saeed Jahdi;Konstantinos Floros;Ingo Lüdtke;Phil Mellor","doi":"10.1109/TDMR.2024.3431707","DOIUrl":"10.1109/TDMR.2024.3431707","url":null,"abstract":"Uneven electro-thermal conditions between parallel-connected devices can reduce the overall reliability of the power electronics systems, particularly during extreme cases such as short circuit. The current distribution between parallel devices is dynamically regulated during the transient and the degradation of devices is intertwined in the long run. To better understand the evolving patterns in the parallel configuration and to compare differences among various device structures, repetitive short circuit tests were conducted on planar, symmetrical double-trench, and asymmetrical trench SiC MOSFETs. Technology computer-aided design (TCAD) models were employed to analyze the evolution of current density and temperature profile between parallel devices. Test results indicate that the switching speed difference caused by gate resistance (Rg) mismatch leads to the asynchronous degradation of asymmetrical trench devices. The decreased threshold voltage (Vth) induce higher short circuit energy (Esc), forming a positive feedback for degradation. Besides, even if the current is dynamically shared between parallel SiC MOSFETs under different case temperature (Tcase), the initial temperature has a key impact on short-circuit reliability over Esc.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"437-447"},"PeriodicalIF":2.5,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141783340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of Critical Working Conditions on Stability of Varistor Characteristics","authors":"Alija Jusić","doi":"10.1109/TDMR.2024.3430033","DOIUrl":"10.1109/TDMR.2024.3430033","url":null,"abstract":"In this paper, the results of the analysis of the influence of critical working conditions on stability of varistor characteristics are presented. Moreover, the paper offers both experimental and theoretical interpretation concerning the influence of temperature, operations’ time-number and the effect of neutron and gamma radiation on the stability of varistor characteristics. For the purpose of this paper an original measuring system of extremely low measurement uncertainty has been developed. Recording of volt-ampere, volt-ohm characteristics as well as varistor, breakdown voltage which was directly measured by a measuring system developed for that purpose, was carried out in the manner based on utilizing a single current pulse. Having analyzed the obtained results, it can be concluded that, when designing the insulation coordination at low or high voltage level, ambient environmental conditions (temperature variation) and functional aging in synergy with natural aging should be taken into account.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"448-455"},"PeriodicalIF":2.5,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Adaptive Read Control Voltage Scheme for Reliability Enhancement of Flash-Based In-Memory Computing Architecture for Neural Network","authors":"Xinrui Zhang;Jian Huang;Xianping Liu;Baiqing Zhong;Zhiyi Yu","doi":"10.1109/TDMR.2024.3429662","DOIUrl":"10.1109/TDMR.2024.3429662","url":null,"abstract":"The storage reliability is critical for flash memory based computing in-memory (CIM) architecture for Convolutional Neural Network (CNN). In this paper, we constructed a CIM scheme based on the Nor Flash array (NFA). We conducted simulations to investigate the impact of threshold voltage distribution and drift of Flash memory cells on the recognition accuracy for various CNN architectures based on the CIM schemes. Based on the reliability study, we proposed a novel compensation scheme to effectively mitigate the impact of threshold voltage drift and evaluated the effectiveness of the proposed scheme by recognition accuracy evaluation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"422-427"},"PeriodicalIF":2.5,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance and Threshold Voltage Reliability of Quaternary InAlGaN/GaN MIS-HEMT on Si for Power Device Applications","authors":"Shivendra K. Rathaur;Cheng-Jun Ma;Abhisek Dixit;Ching-Ting Lee;Edward Yi Chang","doi":"10.1109/TDMR.2024.3429185","DOIUrl":"10.1109/TDMR.2024.3429185","url":null,"abstract":"In this study, we empirically explore the performance degradation of quaternary InAlGaN/AlN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) with a Gate Field Plate (GFP) structure under a Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) stresses. Both stress conditions (PBTI with V\u0000<inline-formula> <tex-math>${_{text {GS}}} = 10$ </tex-math></inline-formula>\u0000 V and NBTI with V\u0000<inline-formula> <tex-math>${_{text {GS}}} {=} -30$ </tex-math></inline-formula>\u0000 V) are applied. The experimental findings reveal a positive shift in threshold voltage (VTH), indicating the presence of a net negative charge beneath the gate area. However, we find distinct degradation dynamics for both stress experiments. During PBTI, the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift remains temperature independent, suggesting the generation of defects leading to electron trapping in the insulator. In NBTI, critical defects are identified, resulting in a permanent \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift with temperature dependence. Furthermore, the extracted activation energy (Ea) from Arrhenius plots in PBTI is determined to be 0.14 eV and 0.11 eV, highlighting the crucial role of shallow C-related traps governed by the Shockley-Read Hall (SRH) recombination process. In contrast, for NBTI, \u0000<inline-formula> <tex-math>${mathrm { E}}_{mathrm { a}} = 0.12$ </tex-math></inline-formula>\u0000 eV, indicating the involvement of surface traps and thermal-assisted de-trapping kinetics, leading to the generation of permanent defects. These results underscore the distinct dynamics of performance degradation phenomena in PBTI and NBTI involves different trap energies at different locations within the device structure.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"428-436"},"PeriodicalIF":2.5,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141720185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on Traps Dynamics & Negative Bias Stress in D-Mode GaN-on-Si Power MIS HEMTs Under High-Temperature","authors":"Shivendra K. Rathaur;Le Trung Hieu;Tsung-Ying Yang;Shang Hua Tsai;Wen Yu Lin;Abhisek Dixit;Edward Yi Chang","doi":"10.1109/TDMR.2024.3426526","DOIUrl":"10.1109/TDMR.2024.3426526","url":null,"abstract":"This experimental study investigates the traps dynamics and threshold voltage (VTH) shift mechanism under negative bias temperature stress for the GaN-on-Si Power MIS HEMTs on field plate design structure. Based on the experimental analysis, two distinct activation energies (Ea) have been identified under the specific reverse bias conditions of VGS= -30 V and VDS=0 V in a wide temperature range. Reverse bias stress experiments (up to 10 ks) show a positive VTH shift of ~1.6 V at room temperature due to the inversion of the charges at the interface between the insulator and AlGaN layer, resulting in net negative charge near the gate region. Subsequently, there is a decrease in VTH shift till \u0000<inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>\u0000 C because of the de-trapping of the inversion charges. This phenomenon shows a strong correlation with a thermally activated activation energy of (E\u0000<inline-formula> <tex-math>${_{text {a}}}~approx ~0.23$ </tex-math></inline-formula>\u0000 eV). Further, the shift in \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 turns negative when the temperature is raised to \u0000<inline-formula> <tex-math>$175~^{circ }$ </tex-math></inline-formula>\u0000 C, indicating the accumulation of electrons in the channel layer with activation energy (E\u0000<inline-formula> <tex-math>${_{text {a}}}~approx ~0.78$ </tex-math></inline-formula>\u0000 eV) attributed to the activation of nitrogen interstitials from the GaN buffer layer. Additionally, the recovery (up to 10 ks) behavior demonstrates the exponential-linear settlement of the traps to recover the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift. Moreover, nitrogen interstitials take more time to suppress the threshold voltage instabilities. These findings explain the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { TH}}$ </tex-math></inline-formula>\u0000 shift mechanisms in GaN-on-Si Power MIS HEMTs under NBTI.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"414-421"},"PeriodicalIF":2.5,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141584947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}