Investigation of Degradation and Failure Mechanism in 1200-V Planar SiC MOSFET Under Statical Accelerated Lifetime Test

IF 2.3 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2025-06-09 DOI:10.1109/TDMR.2025.3577612

J. Tang;Y. Duan;P. Liu

{"title":"Investigation of Degradation and Failure Mechanism in 1200-V Planar SiC MOSFET Under Statical Accelerated Lifetime Test","authors":"J. Tang;Y. Duan;P. Liu","doi":"10.1109/TDMR.2025.3577612","DOIUrl":null,"url":null,"abstract":"The rapid advancement of power electronics applications has propelled the development of SiC MOSFETs while simultaneously posing challenges to their long-term reliability. To address this, the reliability issues associated with long-term stress are comprehensively explored through Accelerated Life Tests’ (ALTs’) verification protocols, aiming to optimize devices and enhance experimental methodologies. 16 sets of ALT experiments were conducted under maximum Tj conditions for HTGB, HTRB, and H3TRB tests, divided into groups around rated voltage conditions. The correlation between stress and degradation is examined by comparing offline data at both 25°C and 175°C. In HTRB tests, precursors of failures are confirmed with further investigation into failure modes. For HTGB experiments, the degradation in the gate oxide under gate bias is characterized using the Tj-Vth and C-V methods. Additionally, the device failures due to HV-H3TRB are analyzed by electrical measurement and acoustic scanning. The experimental findings provide insights that inform the design of subsequent ALT experiments.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"441-451"},"PeriodicalIF":2.3000,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11028914/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

The rapid advancement of power electronics applications has propelled the development of SiC MOSFETs while simultaneously posing challenges to their long-term reliability. To address this, the reliability issues associated with long-term stress are comprehensively explored through Accelerated Life Tests’ (ALTs’) verification protocols, aiming to optimize devices and enhance experimental methodologies. 16 sets of ALT experiments were conducted under maximum Tj conditions for HTGB, HTRB, and H3TRB tests, divided into groups around rated voltage conditions. The correlation between stress and degradation is examined by comparing offline data at both 25°C and 175°C. In HTRB tests, precursors of failures are confirmed with further investigation into failure modes. For HTGB experiments, the degradation in the gate oxide under gate bias is characterized using the Tj-Vth and C-V methods. Additionally, the device failures due to HV-H3TRB are analyzed by electrical measurement and acoustic scanning. The experimental findings provide insights that inform the design of subsequent ALT experiments.

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静态加速寿命试验下1200 v平面SiC MOSFET退化失效机理研究

电力电子应用的快速发展推动了SiC mosfet的发展，同时也对其长期可靠性提出了挑战。为了解决这一问题，通过加速寿命测试（ALTs）验证协议全面探索与长期应力相关的可靠性问题，旨在优化设备并增强实验方法。HTGB、HTRB和H3TRB试验在最大Tj条件下进行16组ALT实验，按额定电压条件分组。通过比较25°C和175°C下的离线数据，研究了应力和降解之间的相关性。在HTRB试验中，通过对失效模式的进一步研究，确定了失效的前兆。对于HTGB实验，采用Tj-Vth和C-V方法表征了栅极偏压下栅极氧化物的降解。此外，通过电测量和声扫描分析了HV-H3TRB引起的设备故障。实验结果为后续ALT实验的设计提供了参考。

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.