A Low Cost Triple-Node-Upset Self-Recoverable Latch Design for Nanoscale CMOS

Due to the constant reduction of semiconductor feature sizes, the charge sharing effect is getting worse. The occurrence probability of triple-node upset (TNU), which has a significant impact on the circuit’s reliability, is rising in nanoscale digital circuits. This paper proposes a low overhead and TNU self-recovery latch (TNU-SR) based on the 28 nm CMOS technology to efficiently tolerate TNU and reduce the power dissipation and latency of the latch. The latch design proposed in this article adopts stacked transistors to reduce sensitive nodes and area overhead. The TNU-SR latch uses clock gating and high-speed transfer path technology, resulting in low power dissipation and low delay. For simulation results, compared with existing latches, it can be known that the TNU-SR latch performs well in terms of delay, power consumption, and area, so it is a good choice for radiation-hardened design for space applications. In addition, compared with the latest TNU self-recovery latch (HLTNURL), the TNU-SR latch proposed in this paper reduces the Power-Area-Delay Product (PADP) metric by 111.13%.