{"title":"Statistical Model and Transistor Size Effect of Hot Carrier Injection for Stability Reinforced SRAM Physically Unclonable Function","authors":"Shufan Xu;Kunyang Liu;Kiichi Niitsu;Hirofumi Shinohara","doi":"10.1109/TDMR.2025.3574796","DOIUrl":null,"url":null,"abstract":"Hot carrier injection (HCI) has been strategically leveraged to enhance the stability of SRAM physically unclonable functions (PUFs). Since the effects of HCI are not constant, exhibiting cell-to-cell variability, a comprehensive distribution model is essential to harness HCI effectively. This article presents a statistical distribution model of mismatch after HCI burn-in and examines the impact of transistor size of PUF on the distribution shape, yielding enhanced stability and shorter HCI burn-in time. The proposed mismatch model after HCI burn-in integrates the native distribution with a Poisson distribution for number of captured electrons and a Gamma distribution for the effect of captured electrons. Model calculations based on size effects reveal that over three times reduction in HCI burn-in duration by enhancing the size to quadruple times: a 15-min for quadruple-size transistor SRAM PUF compared to 46-min for single-size PUF. The model is confirmed by the real chip measurement. The PUFs with several sized transistors are fabricated in a 130-nm standard CMOS process. Experimental results show that quadruple-size transistor SRAM PUF reaches 1.82E−09 unstable cell ratio after 18-min HCI burn-in, which align with the model based expectation. Furthermore, robust stability is exhibited even the worst VT corner (0.6V / <inline-formula> <tex-math>$-40^{\\circ }\\mathrm {C}$ </tex-math></inline-formula>), demonstrating zero bit error (BER<7.81E−08).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"481-491"},"PeriodicalIF":2.3000,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017744","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11017744/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Hot carrier injection (HCI) has been strategically leveraged to enhance the stability of SRAM physically unclonable functions (PUFs). Since the effects of HCI are not constant, exhibiting cell-to-cell variability, a comprehensive distribution model is essential to harness HCI effectively. This article presents a statistical distribution model of mismatch after HCI burn-in and examines the impact of transistor size of PUF on the distribution shape, yielding enhanced stability and shorter HCI burn-in time. The proposed mismatch model after HCI burn-in integrates the native distribution with a Poisson distribution for number of captured electrons and a Gamma distribution for the effect of captured electrons. Model calculations based on size effects reveal that over three times reduction in HCI burn-in duration by enhancing the size to quadruple times: a 15-min for quadruple-size transistor SRAM PUF compared to 46-min for single-size PUF. The model is confirmed by the real chip measurement. The PUFs with several sized transistors are fabricated in a 130-nm standard CMOS process. Experimental results show that quadruple-size transistor SRAM PUF reaches 1.82E−09 unstable cell ratio after 18-min HCI burn-in, which align with the model based expectation. Furthermore, robust stability is exhibited even the worst VT corner (0.6V / $-40^{\circ }\mathrm {C}$ ), demonstrating zero bit error (BER<7.81E−08).
期刊介绍:
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.