Y. Okazaki, T. Kobayashi, S. Konaka, T. Morimoto, M. Takahashi, K. Imai, Y. Kado
{"title":"New well structure for deep sub-μm CMOS/BiCMOS using thin epitaxy over buried layer and trench isolation","authors":"Y. Okazaki, T. Kobayashi, S. Konaka, T. Morimoto, M. Takahashi, K. Imai, Y. Kado","doi":"10.1109/VLSIT.1990.111019","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111019","url":null,"abstract":"Deep submicrometer CMOS devices having a novel well structure using thin epitaxy over a buried n+ layer, a p-type substrate, and trench isolation are proposed. Good isolation characteristics and high latchup immunity are obtained. The thin epitaxial layer, which is necessary for on-chip high-performance bipolar devices, lowers the voltage tolerance of the parasitic vertical bipolar, and causes a new type of latchup phenomena. This must be taken into consideration in p-well design. One-eighth-frequency dividers fabricated to evaluate the new well structure can function up to a maximum operating frequency of 4.2 GHz at 3 V of supply voltage","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126040456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Higashitani, H. Honda, K. Ueda, M. Hatanaka, S. Nagao
{"title":"A novel CBi-CMOS technology by DIIP process","authors":"K. Higashitani, H. Honda, K. Ueda, M. Hatanaka, S. Nagao","doi":"10.1109/VLSIT.1990.111016","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111016","url":null,"abstract":"To realize high performance mixed analog and digital ASICs, a novel CBi-CMOS technology is proposed. This technology, called DIIP (double-implanted and isolated P-well) CBi-CMOS technology, is characterized by a structure with vertical NPN, PNP and CMOS structures on the same chip. In this structure, a vertical PNP transistor and NMOS transistor are fabricated in a P-well, which is isolated from the P-type substrate by the N+ buried layer and has a deep P+ region created by high-energy ion implantation. This deep P+ region acts as a subcollector for the vertical PNP transistor and as a punch-through barrier from the N+ source/drain of the NMOS transistor to the N+ buried layer. Since the P-well is separated from the substrate, a dual power supply can be used for linear circuits","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122970916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Iranmanesh, V. Ilderem, A. Solheim, C. Blair, L. Lam, F. Haas, S. Leibiger, L. Bouknight, R. Lahri, M. Biswal, B. Bastani
{"title":"0.6 μm, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications","authors":"A. Iranmanesh, V. Ilderem, A. Solheim, C. Blair, L. Lam, F. Haas, S. Leibiger, L. Bouknight, R. Lahri, M. Biswal, B. Bastani","doi":"10.1109/VLSIT.1990.111021","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111021","url":null,"abstract":"An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition to silicided poly for local interconnection, this technology offers four layers of metallization with chemical vapor deposition (CVD) tungsten-filled contacts and vias. Interconnection delays are 1 ps/mil. ABiC technology is most attractive for high-performance 50K to 100K gate ECL logic arrays, 100K to 200K gate CMOS/BiCMOS logic arrays, and high-density ASIC products requiring embedded memories","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128522752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Moy, L.K. Wang, D. Seeger, J. Silverman, C. Hu, F. Kaufman, A. Ray, M. Jaso, N. Mazzeo
{"title":"A 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography","authors":"D. Moy, L.K. Wang, D. Seeger, J. Silverman, C. Hu, F. Kaufman, A. Ray, M. Jaso, N. Mazzeo","doi":"10.1109/VLSIT.1990.110982","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110982","url":null,"abstract":"A fully planarized two-level-metal structure has been successfully fabricated at 0.5 μm groundrules with the use of X-ray lithography at all processing levels. A 0.5-μm minimum feature size was required for all levels, including the second-level metal. Planarized PECVD oxide and PECVD nitride were employed as dual dielectric layers below M1 and M2. Chemical vapor deposition (CVD) W studs formed by W etchback served as vertical connections for interlevel vias and contacts. All ten lithography patterning steps were performed with X-ray exposures to determine what possible implications this emerging technology might have on the implementation of the interconnect levels","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Riemenschneider, A. Esquivel, J. Paterson, M. Gill, S. Lin, J. Schreck, D. McElroy, P. Truong, R. Bussey, B. Ashmore, M. McConnell, H. Stiegler, P. Shah
{"title":"A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cell","authors":"B. Riemenschneider, A. Esquivel, J. Paterson, M. Gill, S. Lin, J. Schreck, D. McElroy, P. Truong, R. Bussey, B. Ashmore, M. McConnell, H. Stiegler, P. Shah","doi":"10.1109/VLSIT.1990.111040","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111040","url":null,"abstract":"A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 μm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 μm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 μm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128895692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Drowley, W.M. Huang, P. Vande Voorde, D. Pettengill, J. Turner, A. Kapoor, C. Lin, G. Burton, S. J. Rosner, K. Brigham, H. Fu, S. Oh, M. Scott, S. Chiang, A. Wang
{"title":"STRIPE-a high-speed VLSI bipolar technology featuring self-aligned single-poly base and submicron emitter contacts","authors":"C. Drowley, W.M. Huang, P. Vande Voorde, D. Pettengill, J. Turner, A. Kapoor, C. Lin, G. Burton, S. J. Rosner, K. Brigham, H. Fu, S. Oh, M. Scott, S. Chiang, A. Wang","doi":"10.1109/VLSIT.1990.111004","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111004","url":null,"abstract":"Experimental results are presented for a high-performance silicon bipolar transistor structure utilizing a single layer of polysilicon for both the base and emitter contacts. This structure, called STRIPE (self-aligned trench-isolated polysilicon electrodes), provides a 2.0-μm emitter/base polysilicon contact separation. A 0.4-μm emitter width is achieved with conventional 0.8-μm optical lithography. These dimensions are comparable to those achievable with double-poly structures. Using the STRIPE structure, transistors have been fabricated with cutoff frequency as high as 33.8 GHz","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133793492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Yoneda, Y. Fukuzaki, K. Satoh, Y. Hata, Y. Todokoro, M. Inoue
{"title":"Reliability degradation mechanism of the ultra-thin tunneling oxide by the post-annealing","authors":"K. Yoneda, Y. Fukuzaki, K. Satoh, Y. Hata, Y. Todokoro, M. Inoue","doi":"10.1109/VLSIT.1990.111038","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111038","url":null,"abstract":"The effects of heat treatments on the reliability of ultrathin gate oxide and the mechanism of the reliability degradation are described. Dielectric breakdown reliability of ultrathin tunneling oxide for various post-annealing conditions is discussed. The dielectric breakdown reliability of ultra-thin tunneling oxide is degraded by high-temperature post-annealing. The charge to breakdown is reduced drastically with increasing annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultrathin tunneling oxide by post-annealing can be explained by the tunneling oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultrathin tunneling oxide interface. This increase of roughness is due to the grain growth of the polysilicon gate and viscous flow of oxide, which can be enhanced by increasing the annealing temperature and time","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123969024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Hayashi, S. Wada, K. Kajiyana, K. Oyama, R. Koh, S. Takahashi, T. Kunio
{"title":"Fabrication of three-dimensional IC using `cumulatively bonded IC' (CUBIC) technology","authors":"Y. Hayashi, S. Wada, K. Kajiyana, K. Oyama, R. Koh, S. Takahashi, T. Kunio","doi":"10.1109/VLSIT.1990.111025","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111025","url":null,"abstract":"A technology is proposed for the fabrication of three-dimensional integrated circuits (3D-ICs) having a large number of device layers, referred to as `cumulatively bonded IC' (CUBIC) technology wherein several thin-film devices are bonded cumulatively. The technology was used to fabricate a two-active-layer device having a bulk-Si NMOSFET lower layer and a thinned NMOSFET upper layer. The CUBIC technology, essentially a face-to-back device bonding technology, is applicable to fabricating 3D-ICs having more than three active-device layers. The process consists of two subprocesses-wafer thinning and thin-film lamination. Preferential polishing was used for wafer thinning and bump/tool contacts were used for device-to-device vertical interconnections","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124023118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bryant, B. El-Kareh, T. Furukawa, W. Noble, E. Nowak, W. Tonti
{"title":"A fundamental performance limit of optimized 3.3 V subquarter micron fully overlapped LDD MOSFETs","authors":"A. Bryant, B. El-Kareh, T. Furukawa, W. Noble, E. Nowak, W. Tonti","doi":"10.1109/VLSIT.1990.111000","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111000","url":null,"abstract":"This research reports the direct experimental quantification of the relationship between gate-to-drain capacitance (Cgd) and hot-electron reliability (HER) for fully overlapped lightly-doped-drain (FOLD) n-channel MOSFETs (NFETs). Based on this result it is shown that a peak in device performance occurs at an effective channel length of approximately 0.22 μm for reliable 3.3 V FOLD NFETs having a gate oxide thickness of 10 nm. Below 0.22 μm, performance actually decreases due to the addition of the very large (LDD) regions (fingers) required to maintain adequate HER. This peak shifts to an effective channel length of ≈0.15 μm for asymmetric 3.3-V-FOLD NFETs. Despite this performance limit, it is found that 3.3 V FOLD NFETs are still faster than scaled 2.5-V single-diffusion NFETs down to 0.25 μm. Although a significant performance advantage has been reported for FOLD n-channel MOSFETs, the fundamental tradeoff between parasitic gate-to-drain capacitance and hot electron reliability inherent to the FOLD structure has yet to be quantified. This tradeoff is of critical importance since it limits the performance of FOLD NFETs","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126182357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Role of surface passivation in the integrated processing of MOS structures","authors":"M. Offenberg, M. Liehr, S. Kasi, G. Rubloff","doi":"10.1109/VLSIT.1990.111036","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111036","url":null,"abstract":"Simple MOS capacitors are prepared in a multichamber integrated ultrahigh-vacuum (UHV) processing system with in-situ analysis capabilities. This system has made it possible to integrate the surface preclean steps with the thermal oxidation process without air exposure between the two. In-situ surface analysis has permitted characterization of the precleaned surface, particularly the concentration of oxide and carbon present after different precleaning treatments. The results demonstrate that integration of preclean and oxidation can yield MOS structures with device-quality dielectric breakdown characteristics. Furthermore, they indicate that the role of low-level reactive impurities becomes crucial when using integrated vacuum processing systems. Intentional introduction of a thin passivating oxide layer is essential prior/during wafer heating to oxidation temperature; this prevents degradation of electrical quality which appears associated with etching and roughening of the Si surface by trace O2 impurities","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127133298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}