E. D. Johnson, T. Hook, J. Bertsch, Y. Taur, C. Chen, H.J. Shin, S. Ramaswamy, A. Edenfeld, C. Alcorn
{"title":"A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices","authors":"E. D. Johnson, T. Hook, J. Bertsch, Y. Taur, C. Chen, H.J. Shin, S. Ramaswamy, A. Edenfeld, C. Alcorn","doi":"10.1109/VLSIT.1990.111022","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111022","url":null,"abstract":"A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while keeping the CMOS devices at 3.3 V for reliable operation. With such a circuit, performance gain over CMOS is achieved at a reduced channel length and voltage. This demonstrates the feasibility of scaling BiCMOS technology to reduced channel length and power supply voltage","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124886531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K.T. Kim, L.G. Kang, T. Park, Y. Shin, J. Park, C.J. Lee, C. Hwang, D. Chin, Y.E. Park
{"title":"Tungsten silicide/titanium nitride compound gate for submicron CMOSFET","authors":"K.T. Kim, L.G. Kang, T. Park, Y. Shin, J. Park, C.J. Lee, C. Hwang, D. Chin, Y.E. Park","doi":"10.1109/VLSIT.1990.111035","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111035","url":null,"abstract":"Experimental results are presented for a WSi2/TiN compound-gate MOSFET with a near-midgap work function ranging from 4.63 to 4.75 eV and low resistivity. Sheet resistances of the compound gate and the conventional n+ gate with and without the interconnection layer are studied, and it is shown that the compound gate materials are an adequate interconnection layer. When positive bias is applied to the gate, the tunneling current of a compound-gate MOS is similar to that of an n+-poly-gate MOS with and without interconnection layer. This is because electrons are tunneling through the oxide from the silicon substrate to the gate, so that the barrier height is defined dominantly by the oxide barrier from the silicon substrate","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125953764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Drain-structure design for reduced band-to-band and band-to-defect tunneling leakage","authors":"T. Hori","doi":"10.1109/VLSIT.1990.111012","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111012","url":null,"abstract":"The author investigates and models gate-induced drain leakage (GIDL) effects over a wide variety of drain structures, including <e1>n </e1><sup>+</sup>-As/<e1>n</e1><sup>-</sup>-P combinations, <e1>n</e1> <sup>-</sup> implant doses (<e1>N</e1><sub>n-</sub>), and spacer lengths (L<sub>s</sub>). An analytical model taking account of nm-order As doping modulation is proposed to explain the enhanced GIDL for <e1>n</e1><sup>+</sup>-As FETs and the suppressed B-B tunneling with increasing <e1>N</e1><sub>n-</sub> for large-tilt-angle implanted-drain devices. Band-to-defect tunneling via interface states is also simulated and found to limit device performance, as well as hot-carrier reliability, much more severely than B-B tunneling. Based on the above understanding, drain-structure design is discussed in view of both performance and reliability","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}