E. D. Johnson, T. Hook, J. Bertsch, Y. Taur, C. Chen, H.J. Shin, S. Ramaswamy, A. Edenfeld, C. Alcorn
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引用次数: 11
摘要
介绍了一种基于优化的3.3 v 0.5 μ m CMOS基制程的BiCMOS技术。一个高性能的单多晶硅npn晶体管的截止频率为15 GHz，集成了cmos兼容的热循环。采用新颖的电平移位BiCMOS电路技术，使双极器件在更高的电压(4.1 V)下工作而不降低性能，同时将CMOS器件保持在3.3 V以可靠运行。使用这样的电路，可以在减少通道长度和电压的情况下获得优于CMOS的性能增益。这证明了缩小BiCMOS技术以减小通道长度和电源电压的可行性
A high-performance 0.5-μm BiCMOS technology with 3.3-V CMOS devices
A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while keeping the CMOS devices at 3.3 V for reliable operation. With such a circuit, performance gain over CMOS is achieved at a reduced channel length and voltage. This demonstrates the feasibility of scaling BiCMOS technology to reduced channel length and power supply voltage
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