Digest of Technical Papers.1990 Symposium on VLSI Technology最新文献_第6页

Process technologies for a 16 ns high speed 1 Mb CMOS EPROM 16ns高速1mb CMOS EPROM的工艺技术

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111041

N. Matsukawa, H. Araki, K. Narita, K. Masuda, S. Atsumi, M. Kuriyama, K. Imamiya

引用次数: 0

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted P+ gate p-channel MOSFETs 硅栅微结构和栅氧化工艺对BF2注入P+栅P沟道mosfet阈值电压不稳定性的影响

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111033

Hsing-Huang Tseng Hsing-Huang Tseng, P. Tobin, F. Baker, J. Pfiester, K. Evans, P. Fejes

{"title":"The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted P+ gate p-channel MOSFETs","authors":"Hsing-Huang Tseng Hsing-Huang Tseng, P. Tobin, F. Baker, J. Pfiester, K. Evans, P. Fejes","doi":"10.1109/VLSIT.1990.111033","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111033","url":null,"abstract":"A study of the effects of P+ poly gate microstructure and gate oxide cycle on boron penetration from gate electrode through thin oxide is reported. The boron diffusion and the trap generation in the oxide can be significantly reduced by using an as-deposited amorphous Si gate and an oxide cycle which incorporates less Cl into the film. A strong interaction between fluorine and boron results in boron penetration into the channel and electron trap generation in the oxide. A larger grain size means fewer grain boundaries are available for boron and fluorine diffusion from the P+ gate to oxide. Less fluorine in the oxide results in less electron trap generation and less boron penetration to the Si substrate. A smaller content of Cl in the oxide results in a reduction of boron penetration. Finally, a co-implant of boron and fluorine into the as-deposited amorphous Si gate results in minimum boron diffusion into the Si substrate, which may provide the control of fluorine dose needed to reduce the interface trap density between oxide/Si interface. Increasing the grain size of the poly gate as reported above can be applied to reduce the large concentration of fluorine introduced into the gate oxide by other processes such as CVD tungsten polycide technology","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123507847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs 用于4mbit和更高密度sram的TFT(薄膜晶体管)单元技术

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110989

M. Kinugawa, M. Kakumu, T. Yoshida, T. Nakayama, S. Morita, K. Kubota, F. Matsuoka, H. Oyamatsu, K. Ochii, K. Maeguchi

{"title":"TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs","authors":"M. Kinugawa, M. Kakumu, T. Yoshida, T. Nakayama, S. Morita, K. Kubota, F. Matsuoka, H. Oyamatsu, K. Ochii, K. Maeguchi","doi":"10.1109/VLSIT.1990.110989","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110989","url":null,"abstract":"Thin-film transistor (TFT) cell technology has been proposed for high-density SRAM cells. It was demonstrated that when utilizing this technology both low standby current and high cell stability are obtained simultaneously without increasing cell size. TFT characteristics required for 4-Mb SRAMs are discussed, and it is noted that improvements in packing density while maintaining low standby current cause difficulties in achieving stable cell characteristics in very-high-density SRAMs using a conventional high-resistance load cell (Hi-R cell). In SRAMs with feature size of 0.5 μm or less, operation voltage is lowered due to severe hot-carrier-induced degradation in MOSFETs. To achieve desirable characteristics for future SRAMs, the grain size dependence of TFT characteristics was investigated. It is shown that low-temperature regrowth of α-Si is a promising method to obtain very large grain size, resulting in excellent TFT characteristics. TFT technology was applied to a 4-Mb SRAM with a new cell structure, where the drain regions of driver transistors form gate electrodes for TFTs. The 4-Mb SRAM was successfully fabricated, verifying the feasibility and validity of the TFT technology","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Perimeter and plug effects in deep sub-micron polysilicon emitter bipolar transistors 深亚微米多晶硅发射极双极晶体管的周长和插头效应

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111005

J. Burghartz, J. Sun, S. Mader, C. Stanis, B. Ginsberg

引用次数: 19

A new MOSFETs degradation induced by gate current in off-state condition 一种由栅极电流引起的新型mosfet失态退化

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111014

K. Yoshikawa, N. Arai, S. Mori, Y. Kaneko, Y. Ohshima, K. Narita, H. Araki

引用次数: 1

Selective and nonselective deposition of aluminum by LPCVD using DMAH and microregion observation of single crystal aluminum with scanning μ-RHEED microscope 用DMAH选择性和非选择性LPCVD沉积铝，用扫描μ-RHEED显微镜观察单晶铝的微区

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110980

K. Tsubouchi, K. Masu, N. Shigeeda, T. Matano, Y. Hiura, N. Mikoshiba, S. Matsumoto, T. Asaba, T. Marui, T. Kajikawa

引用次数: 8

A 26 ps self-aligned epitaxial silicon base bipolar technology 一种26ps自对准外延硅基双极技术

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111003

J. Comfort, P. Lu, D. Tang, T. Chen, J. Sun, B. Meyerson, W. Lee, J. Warnock, J. Cressler, K. Toh, J. Cotte

引用次数: 8

Buried bit-line cell for 64 Mb DRAMs 埋位线单元为64 Mb的dram

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110986

Y. Kohyama, T. Yamamoto, A. Sudo, T. Watanabe, T. Tanaka

引用次数: 1

Electromigration characteristics of via chains for multilayered metallization 多层金属化孔链的电迁移特性

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110995

K. Okuyama, T. Fujii, Y. Tanigaki, R. Nagai

引用次数: 2

Photo assisted LPCVD TiN for deep submicron contacts using organo-titanium compound 利用有机钛化合物光辅助LPCVD TiN用于深亚微米接触

Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111008

K. Ikeda, M. Maeda, Y. Arita

引用次数: 2