Buried bit-line cell for 64 Mb DRAMs

The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7F², where F is the lithographic feature size. A 2.25-μm² cell area is achieved using a 0.51-μm feature size. A 1.4-μm² cell area is attainable using a 0.4-μm feature size. The memory-cell vertical size (2F) includes a line and space for a trench isolation pattern in which the buried bit-line is formed. The horizontal size (4F+a) includes two word-line line and space pairs and a word-line to bit-line contact alignment tolerance denoted by a. A storage node contact is self-aligned to the word-line. Since the a is considered to be less than F/2, a cell area of less than 9F² is realized. If the bit-line contact is also self-aligned to the word-line, an 8F² cell area can in theory be realized