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Digest of Technical Papers.1990 Symposium on VLSI Technology最新文献

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A high-performance stacked-CMOS SRAM cell by solid phase growth technique 基于固相生长技术的高性能叠层cmos SRAM电池
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110988
Y. Uemoto, E. Fujii, A. Nakamura, K. Senda
{"title":"A high-performance stacked-CMOS SRAM cell by solid phase growth technique","authors":"Y. Uemoto, E. Fujii, A. Nakamura, K. Senda","doi":"10.1109/VLSIT.1990.110988","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110988","url":null,"abstract":"A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the logic swing of 3 V, which could satisfy a 4-Mb SRAM with standby-current of 0.3 μA. The high performance has been attained as a result of enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a novel solid-phase growth (SPG) technique","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123505288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Suppressing stress-induced and electromigration failures with Al/Al stacked structure Al/Al叠层结构抑制应力诱导和电迁移失效
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110991
S. Shima, H. Ito, S. Shingubara
{"title":"Suppressing stress-induced and electromigration failures with Al/Al stacked structure","authors":"S. Shima, H. Ito, S. Shingubara","doi":"10.1109/VLSIT.1990.110991","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110991","url":null,"abstract":"A Al/Al stacked multilayered interconnection that can suppress both stress-induced and electromigration failures without barrier metal was developed. Stress-induced failures are almost completely suppressed and electromigration lifetime is improved more than four times. The higher reliability mechanism is explained in terms of graphed results of the microstructure and mechanical properties","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL SST-BiCMOS技术，130 ps CMOS和50 ps ECL
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111020
Y. Kobayashi, C. Yamaguchi, N. Shimoyama, Y. Tanabe, K. Miura, S. Nakajima, K. Imai, T. Sakai
{"title":"SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL","authors":"Y. Kobayashi, C. Yamaguchi, N. Shimoyama, Y. Tanabe, K. Miura, S. Nakajima, K. Imai, T. Sakai","doi":"10.1109/VLSIT.1990.111020","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111020","url":null,"abstract":"A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of 130 ps/gate, two-input NAND CMOS, and 50-ps/gate emitter-coupled logic (ECL) on a single chip. The SST-BiCMOS structure and its characteristics and device performance are presented","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Formation of ultra-shallow low-reverse current n+p junctions by 450°C furnace annealing 450℃炉退火形成超浅低反向电流n+p结
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111009
T. Shibata, A. Okita, Y. Kato, T. Ohmi, T. Nitta
{"title":"Formation of ultra-shallow low-reverse current n+p junctions by 450°C furnace annealing","authors":"T. Shibata, A. Okita, Y. Kato, T. Ohmi, T. Nitta","doi":"10.1109/VLSIT.1990.111009","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111009","url":null,"abstract":"Experimental results are reported of the successful formation of ultra-shallow low-reverse-current junctions by arsenic implantation followed by furnace annealing at 450°C. The junction depth and the sheet resistance of the 450°C annealed junctions are 60 nm and 150 Ω/square, respectively. The reverse bias current at -5 V is 1.5×10-7 A/cm2, which is about three orders of magnitude smaller than previously reported data. These results were obtained by an ultraclean ion implantation technology in which wafer surface contamination during the ion implantation process has been largely eliminated","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"152 3723 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132936141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SiGe-base PNP transistors fabricated with n-type UHV/CVD LTE in a `No Dt' process 用n型UHV/CVD LTE在“No Dt”工艺中制备sige基PNP晶体管
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111001
D. Harame, J. Stork, B. Meyerson, E. Crabbé, G. Patton, G. Scilla, E. de Fresart, A. Bright, C. Stanis, A. Megdanis, M. Manny, E. Petrillo, M. Dimeo, R. Mcintosh, K. Chan
{"title":"SiGe-base PNP transistors fabricated with n-type UHV/CVD LTE in a `No Dt' process","authors":"D. Harame, J. Stork, B. Meyerson, E. Crabbé, G. Patton, G. Scilla, E. de Fresart, A. Bright, C. Stanis, A. Megdanis, M. Manny, E. Petrillo, M. Dimeo, R. Mcintosh, K. Chan","doi":"10.1109/VLSIT.1990.111001","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111001","url":null,"abstract":"Experimental results are presented on the use of N-type ultrahigh-vacuum/chemical vapor deposition (UHV/CVD) low-temperature epitaxy (LTE) to deposit thin (45 nm), heavily doped (1×1019 cm-3) SiGe films to form the base of PNP transistors. To take full advantage of epitaxial base technology, the thermal cycles following the base deposition that cause dopant diffusion and relaxation of highly strained layers must be eliminated. This objective is met by a novel process using PECVD insulators and UHV/CVD LTE emitter deposition to limit the temperature following the base deposition to 550°C. This is essentially a `No Dt' process in the sense that the effective dopant diffusion length Dt is negligible at this temperature. An advanced double-polysilicon bipolar structure was modified to fabricate non-self-aligned small-geometry transistors. Both DC and AC measurements were used to characterize the devices, confirming the presence of a large valence band offset at the base-collector junction. The resulting barrier to minority carrier transport caused additional charge storage in the neutral base and limited the peak cutoff frequency to 15 GHz independent of collector doping. The results demonstrate the impact of the valence band offset of SiGe heterojunctions on the performance of PNP transistors","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130403771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load 采用双门自对准多晶硅PMOS薄膜晶体管(TFT)负载的半微米SRAM电池
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110987
A. Adan, K. Suzuki, H. Shibayama, R. Miyake
{"title":"A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load","authors":"A. Adan, K. Suzuki, H. Shibayama, R. Miyake","doi":"10.1109/VLSIT.1990.110987","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110987","url":null,"abstract":"An SRAM cell structure using stacked double-gated, self-aligned polysilicon PMOS thin-film transistors (TFT) is described. This memory cell has been realized in a half-micron, triple-poly, double-metal CMOS process; the cell area is 22.32 μm2, adequate for 4-Mb SRAMs. The main features are: (i) self-aligned structure to precisely define the TFT channel, (ii) TFT drive current enhancement by double gate effect, and (iii) the realization of sub-micron channel length TFTs, which demonstrates the feasibility of this cell for the next-generation 16-Mb SRAM","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Device performance analysis using Monte-Carlo simulator for SOI MOS transistors on solid-phase-recrystallized silicon films 基于蒙特卡罗模拟器的固体相再结晶硅薄膜SOI MOS晶体管器件性能分析
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111032
S. Kambayashi, I. Mizushima, M. Kemmochi, H. Kawaguchi, S. Shima, H. Kuwano, S. Onga, J. Matsunaga
{"title":"Device performance analysis using Monte-Carlo simulator for SOI MOS transistors on solid-phase-recrystallized silicon films","authors":"S. Kambayashi, I. Mizushima, M. Kemmochi, H. Kawaguchi, S. Shima, H. Kuwano, S. Onga, J. Matsunaga","doi":"10.1109/VLSIT.1990.111032","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111032","url":null,"abstract":"A Monte Carlo simulator has been developed that can trace random nucleation and regrowth characteristics for silicon-on-insulator MOS transistors and can predict the distribution of device characteristics. Activation energies for nucleation and regrowth in solid-phase were derived to be 3.9 eV and 2.8 eV, respectively. Localized states caused by the regrowth boundary were observed as a function of regrown grain size where values were two orders of magnitude larger than for bulk MOS. Threshold voltage shift and carrier mobility could be interpreted mainly in terms of the density-of-states and boundary structure; the distribution of threshold voltage and mobility were predicted closely by the Monte Carlo simulator","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127386004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Merged complementary BiCMOS for logic applications 用于逻辑应用的合并互补BiCMOS
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111018
S. Ogura, N. Rovedo, J. Acocella, A. Dally, T. Yanagisawa, J. Burkhardt, T. Buti, C. Richwine, F. Montegari, K. Barnes, C. Ng, E. Valsamakis, C. Codella
{"title":"Merged complementary BiCMOS for logic applications","authors":"S. Ogura, N. Rovedo, J. Acocella, A. Dally, T. Yanagisawa, J. Burkhardt, T. Buti, C. Richwine, F. Montegari, K. Barnes, C. Ng, E. Valsamakis, C. Codella","doi":"10.1109/VLSIT.1990.111018","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111018","url":null,"abstract":"The deficiencies of BiCMOS logic are analyzed, and the addition of a high-performance vertical pnp to the BiCMOS technology, henceforth called complementary BiCMOS technology, is considered as a solution. It is suggested that density problems associated with BiCMOS logic can be alleviated by replacing the conventional BiCMOS logic circuit, i.e. the `totem-pole' circuit, with a simpler complementary emitter follower circuit. This circuit allows the use of a merged bipolar-FET device structure as well as a common subcollector for the pnp, which further increases density. Another benefit of the common subcollector is that it reduces the process complexity associated with the addition of the vertical pnp. High performance is demonstrated with results from a test circuit with delays of 250 pS with 0.3 pF loading","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126294957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Effect of stress in passivation layer on electromigration lifetime for vias 钝化层应力对过孔电迁移寿命的影响
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110993
H. Nishimura, Y. Okuda, T. Ueda, M. Hirata, K. Yano
{"title":"Effect of stress in passivation layer on electromigration lifetime for vias","authors":"H. Nishimura, Y. Okuda, T. Ueda, M. Hirata, K. Yano","doi":"10.1109/VLSIT.1990.110993","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110993","url":null,"abstract":"The electromigration performance of the 1.2-μm-diameter via chain between two levels of an Al line was evaluated. It was found that the electromigration lifetime of the vias decreases owing to the increase in the total compressive stress in the passivation layer, even though the step coverage of Al film in the vias is improved by controlling the slope angle of the via hole to increase the electromigration lifetime. On the other hand, the lower limit of the step coverage of Al film in the vias is determined by the stress-induced failure rate. Therefore, in order to bring about high reliability of the vias, the total compressive stress in the passivation layer must be lowered and the step coverage of Al film in the vias must be improved","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134264131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Very shallow p+-n junctions and subquarter micron gate p-channel MOSFETs 极浅p+-n结和亚四分之一微米栅p沟道mosfet
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111010
S. Ando, H. Horie, M. Imai, K. Oikawa, H. Kato, H. Ishiwari, S. Hijiya
{"title":"Very shallow p+-n junctions and subquarter micron gate p-channel MOSFETs","authors":"S. Ando, H. Horie, M. Imai, K. Oikawa, H. Kato, H. Ishiwari, S. Hijiya","doi":"10.1109/VLSIT.1990.111010","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111010","url":null,"abstract":"Fabricating shallow p+-n junctions by low energy BF2 implantation, especially using furnace annealing, requires preamorphous implantation of crystalline silicon to eliminate the boron channeling and the suppression of diffusion in heat cycles. A preimplantation technique is presented that uses fluorine to influence the electric characteristics of p-channel MOSFETs. Using heat cycling of 850°C for 10 min, a junction depth of 80 nm and sheet resistance of 400 Ω was achieved. The boron profile after annealing is close to a bell shape, like the profile obtained by boron-only implantation. Lowering preimplantation energy is found to increase the excess vacancy density in the region of high boron concentration and increases diffusion there","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131142344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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