{"title":"基于固相生长技术的高性能叠层cmos SRAM电池","authors":"Y. Uemoto, E. Fujii, A. Nakamura, K. Senda","doi":"10.1109/VLSIT.1990.110988","DOIUrl":null,"url":null,"abstract":"A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the logic swing of 3 V, which could satisfy a 4-Mb SRAM with standby-current of 0.3 μA. The high performance has been attained as a result of enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a novel solid-phase growth (SPG) technique","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A high-performance stacked-CMOS SRAM cell by solid phase growth technique\",\"authors\":\"Y. Uemoto, E. Fujii, A. Nakamura, K. Senda\",\"doi\":\"10.1109/VLSIT.1990.110988\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the logic swing of 3 V, which could satisfy a 4-Mb SRAM with standby-current of 0.3 μA. The high performance has been attained as a result of enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a novel solid-phase growth (SPG) technique\",\"PeriodicalId\":441541,\"journal\":{\"name\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1990.110988\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.110988","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high-performance stacked-CMOS SRAM cell by solid phase growth technique
A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the logic swing of 3 V, which could satisfy a 4-Mb SRAM with standby-current of 0.3 μA. The high performance has been attained as a result of enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a novel solid-phase growth (SPG) technique
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