A high-performance stacked-CMOS SRAM cell by solid phase growth technique

Abstract

A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the logic swing of 3 V, which could satisfy a 4-Mb SRAM with standby-current of 0.3 μA. The high performance has been attained as a result of enlarging the grain size of the polysilicon film for the active region of the p-ch TFT by a novel solid-phase growth (SPG) technique