Y. Kobayashi, C. Yamaguchi, N. Shimoyama, Y. Tanabe, K. Miura, S. Nakajima, K. Imai, T. Sakai
{"title":"SST-BiCMOS技术，130 ps CMOS和50 ps ECL","authors":"Y. Kobayashi, C. Yamaguchi, N. Shimoyama, Y. Tanabe, K. Miura, S. Nakajima, K. Imai, T. Sakai","doi":"10.1109/VLSIT.1990.111020","DOIUrl":null,"url":null,"abstract":"A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of 130 ps/gate, two-input NAND CMOS, and 50-ps/gate emitter-coupled logic (ECL) on a single chip. The SST-BiCMOS structure and its characteristics and device performance are presented","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL\",\"authors\":\"Y. Kobayashi, C. Yamaguchi, N. Shimoyama, Y. Tanabe, K. Miura, S. Nakajima, K. Imai, T. Sakai\",\"doi\":\"10.1109/VLSIT.1990.111020\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of 130 ps/gate, two-input NAND CMOS, and 50-ps/gate emitter-coupled logic (ECL) on a single chip. The SST-BiCMOS structure and its characteristics and device performance are presented\",\"PeriodicalId\":441541,\"journal\":{\"name\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1990.111020\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.111020","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SST-BiCMOS technology with 130 ps CMOS and 50 ps ECL
A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of 130 ps/gate, two-input NAND CMOS, and 50-ps/gate emitter-coupled logic (ECL) on a single chip. The SST-BiCMOS structure and its characteristics and device performance are presented
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
