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Digest of Technical Papers.1990 Symposium on VLSI Technology最新文献

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A ferroelectric DRAM cell for high density NVRAMs 一种用于高密度nvram的铁电DRAM单元
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110985
R. Moazzami, Chen Ming Hu Chen Ming Hu, W. Shepherd
{"title":"A ferroelectric DRAM cell for high density NVRAMs","authors":"R. Moazzami, Chen Ming Hu Chen Ming Hu, W. Shepherd","doi":"10.1109/VLSIT.1990.110985","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110985","url":null,"abstract":"The operation of a ferroelectric memory cell for nonvolatile random access memory (NVRAM) applications is described. Because ferroelectric polarization reversal only occurs during store/recall but not DRAM read/write, ferroelectric fatigue is not a serious endurance problem. In the worst case, the effective silicon dioxide thickness of the unoptimized film studied here is less than 15 Å. The resistivity and endurance properties of the ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very high density nonvolatile RAM with practically no read/write cycle limit and at least 1010 nonvolatile store/recall cycles","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127554160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Analysis of an ONO gate film effect on n- and p-MOSFET mobilities ONO栅极膜对n-和p-MOSFET迁移率的影响分析
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111043
H. Iwai, H. Momose, S. Takagi, T. Morimoto, S. Kitagawa, S. Kambayashi, K. Yamabe, S. Onga
{"title":"Analysis of an ONO gate film effect on n- and p-MOSFET mobilities","authors":"H. Iwai, H. Momose, S. Takagi, T. Morimoto, S. Kitagawa, S. Kambayashi, K. Yamabe, S. Onga","doi":"10.1109/VLSIT.1990.111043","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111043","url":null,"abstract":"The effect of the nitrogen atoms in the gate oxide and why gate oxide nitridation acts oppositely on the n- and p-MOSFET mobilities were studied. It was found that the mobility changes for the oxide/nitride/oxide (ONO) gate MOSFETs are not caused by the high-temperature process during the rapid thermal process (RTP), but rather are caused by the involvement of the nitrogen atoms in the gate oxide. The interfacial structures were observed by TEM. Although some interfacial structure difference was observed, there was no major difference in surface roughness between `PO' and `NO' samples. The opposite effect of the ONO gate films on the n- and p-MOSFET mobilities cannot be explained completely by a donor layer formation by the nitrogen diffusion into the substrate. The effect might be explained by the residual mechanical stress caused by the involvement of the nitrogen atoms in the gate oxide","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"382 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122784209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A utility-based integrated process simulation system 基于实用程序的集成过程仿真系统
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111026
E. W. Scheckler, A. Wong, R.H. Wang, G. Chin, J. Camagna, K. Toh, K. Tadros, R. Ferguson, A. Neureuther, R. Dutton
{"title":"A utility-based integrated process simulation system","authors":"E. W. Scheckler, A. Wong, R.H. Wang, G. Chin, J. Camagna, K. Toh, K. Tadros, R. Ferguson, A. Neureuther, R. Dutton","doi":"10.1109/VLSIT.1990.111026","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111026","url":null,"abstract":"The effectiveness of a utility-based process simulation system is demonstrated by investigating several current VLSI technology problems with a variety of powerful simulators. Interactions of deposition, etching and spin-on steps in a planarization process are investigated with topography and creeping flow simulators. Topography and thermal processing simulators are combined to investigate a complete bipolar device process. Simulators for 2-D image calculation and scattering from topography are applied to problems in submicron lithography. The primary platform used for utility-based software integration is SIMPL-DIX which connects layout and process flow data, and an X-window graphical user-interface, into a system for generating device cross-sections. An experimental adaptation of SIMPL into the OCT/VEM/RPC CAD framework has also been developed that provides access to the VEM user-interface, the OCT database, a mask editor, and circuit CAD tools","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
ECR position etching for high selectivity and high-rate N+ poly-Si patterning ECR位置蚀刻用于高选择性和高速率N+多晶硅图像化
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110978
S. Samukawa, M. Sasaki, Y. Suzuki, S. Mori
{"title":"ECR position etching for high selectivity and high-rate N+ poly-Si patterning","authors":"S. Samukawa, M. Sasaki, Y. Suzuki, S. Mori","doi":"10.1109/VLSIT.1990.110978","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110978","url":null,"abstract":"A novel electron cyclotron resonance (ECR) plasma etching technology is described that produces simultaneously highly selective, high-rate, and anisotropic n+ poly-Si etching at a low acceleration voltage. ECR position etching for n+ poly-Si pattern fabrication is discussed. In this technology, a substrate is located at the ECR position in a plasma chamber, and etching is carried out without RF bias power. Due to the low ion energy, high ion current and highly collimated ion flux at the ECR position, n+ poly-Si etching with a high selectivity and a high rate can be realized. The n+ poly-Si etching rate at the ECR position is 3300 A/min, and an anisotropic etching profile is realized by using Cl2 etching gas. The selectivity ratio of n+ poly-Si to SiO2 etching is 260. These etching characteristics are explained by low ion energy, high ion current density and highly collimated ion flux at the ECR position","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124014360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved yield and reliability in aluminum interconnects through fluorine incorporation 通过加氟提高铝互连的良率和可靠性
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110994
K. Macwilliams, L. Lowry, M. Isaac, D. Cobert, T. Zietlow
{"title":"Improved yield and reliability in aluminum interconnects through fluorine incorporation","authors":"K. Macwilliams, L. Lowry, M. Isaac, D. Cobert, T. Zietlow","doi":"10.1109/VLSIT.1990.110994","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110994","url":null,"abstract":"It is argued that the substantial reduction in hillock formation with F (fluorine) incorporation (relative to Cu incorporation) is predominantly due to the reactive nature of the F. The highly electronegative fluorine forms a much stronger chemical bond than aluminum with itself or aluminum with Cu, which acquires its beneficial effects from forming Cu precipitates at grain boundaries. Due to the significant improvement in hillock formation behavior with these very small F incorporations, it seems that electromigration and stress-induced voiding could also be reduced by a similar technique. Test data leading to these conclusions are presented","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115355248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
63-75 GHz fT SiGe-base heterojunction bipolar technology 63-75 GHz fT硅基异质结双极技术
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111002
G. Patton, J. Comfort, B. Meyerson, E. Crabbé, G. Scilla, E. D. Frésart, J. Stork, J. Sun, D. Harame, J. Burghartz
{"title":"63-75 GHz fT SiGe-base heterojunction bipolar technology","authors":"G. Patton, J. Comfort, B. Meyerson, E. Crabbé, G. Scilla, E. D. Frésart, J. Stork, J. Sun, D. Harame, J. Burghartz","doi":"10.1109/VLSIT.1990.111002","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111002","url":null,"abstract":"Experimental results for maximum cut-off frequency (fT) values of 75 and 52 GHz were achieved for SiGe-base and Si-base bipolar transistors with intrinsic base sheet resistances in the 10-17 kΩ/square range. These results extend the speed of silicon bipolar devices into a regime previously reserved to GaAs and other compound semiconductor technologies. Excellent junction characteristics were also obtained for devices as large as 100000 μm2 and for current densities as high as 106 A/cm2. The performance levels obtained for the SiGe transistors, which contain less than 10% germanium in the base, represent almost a factor of two increase in the speed of a Si bipolar transistor. These results demonstrate the significant performance advantage offered by SiGe heterojunction technology","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"41 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129140100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Superconducting interconnects for VLSI multi-chip system integration 用于VLSI多芯片系统集成的超导互连
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111007
B. Langley, R. Pease
{"title":"Superconducting interconnects for VLSI multi-chip system integration","authors":"B. Langley, R. Pease","doi":"10.1109/VLSIT.1990.111007","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111007","url":null,"abstract":"Results related to the fabrication and measurement of the propagation constant of superconducting microstrip lines operating at microwave frequencies are presented. The phase velocity and penetration depth measurements lead to several conclusions regarding the use of superconducting transmission lines as off-chip interconnects. First, the line's phase velocity can be determined from simple formulas, which greatly aids in interconnect design. The magnitude of the phase velocity is determined mostly by the effective dielectric constant, except for lines with dielectric thickness on the order of the penetration depth, for which the phase velocity is degraded. Attenuation constant measurements were also done. The low-temperature attenuation level is 2×10-4 dB/cm at 2.3 GHz even though a poor-quality film was used. This residual attenuation level at low temperature is probably dominated by dielectric losses since it is proportional to frequency; this suggests that the superconductor losses are less than this level","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high performance 16-Mb DRAM technology 采用高性能16mb DRAM技术
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110983
P. Bakeman, A. Bergendahl, M. Hakey, D. Horak, S. Luce, B. Pierson
{"title":"A high performance 16-Mb DRAM technology","authors":"P. Bakeman, A. Bergendahl, M. Hakey, D. Horak, S. Luce, B. Pierson","doi":"10.1109/VLSIT.1990.110983","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110983","url":null,"abstract":"A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstrated","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Two-dimensional simulation of band-to-band tunneling in an LDD-MOSFET: explanation of experimental results and prediction of new phenomena LDD-MOSFET中带对带隧穿的二维模拟:实验结果的解释和新现象的预测
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111011
M. Orlowski, S. Sun, P. Blakey, R. Subrahmanyan
{"title":"Two-dimensional simulation of band-to-band tunneling in an LDD-MOSFET: explanation of experimental results and prediction of new phenomena","authors":"M. Orlowski, S. Sun, P. Blakey, R. Subrahmanyan","doi":"10.1109/VLSIT.1990.111011","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111011","url":null,"abstract":"A generalization of band-to-band tunneling (BTBT) in two dimensions was implemented using a MINIMOS device simulator. The BTBT-related leakage currents of a MOSFET were simulated as functions of drain/gate bias, oxide thickness, and lightly-doped drain (LDD) structure and found to be in agreement with experiment. It is found that in the deep subthreshold regime at high drain voltage, the leakage currents result from the combined effects of BTBT and impact ionization. The model allows a quantitative explanation of the recently reported enhanced transistor degradation due to BTBT. In addition, a new mode of BTBT-related leakage for deep-submicron MOSFETs in the entire channel region is predicted","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132541154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Non-invasive process temperature monitoring using laser-acoustic techniques 利用激光声学技术进行无创过程温度监测
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111030
Y.J. Lee, C. Chou, B. Khuri-Yakub, K. Saraswat
{"title":"Non-invasive process temperature monitoring using laser-acoustic techniques","authors":"Y.J. Lee, C. Chou, B. Khuri-Yakub, K. Saraswat","doi":"10.1109/VLSIT.1990.111030","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111030","url":null,"abstract":"A method of temperature measurement is studied that is suitable for in situ monitoring of semiconductor wafer temperature, based on the temperature dependence of acoustic waves. The change in the dispersion relations of the plate modes through the wafer as a function of temperature is exploited to provide a viable temperature-monitoring scheme with advantages over both thermocouples and pyrometers. Temperature based on the velocity dependence of acoustic waves through a thin layer of ambient directly above the silicon wafer is expected to be important in better controlling processes where the mass transport mechanisms and the effects of stagnant layers play a significant part in the process. The information about the temperature of the layer of ambient can also be used to obtain the wafer bulk temperature. Because of the high temperature sensitivity of the acoustic wave velocity in gases, this system can be used as a practical in situ temperature measurement scheme with sensitivities better than ±1°C","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121103387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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