P. Bakeman, A. Bergendahl, M. Hakey, D. Horak, S. Luce, B. Pierson
{"title":"采用高性能16mb DRAM技术","authors":"P. Bakeman, A. Bergendahl, M. Hakey, D. Horak, S. Luce, B. Pierson","doi":"10.1109/VLSIT.1990.110983","DOIUrl":null,"url":null,"abstract":"A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstrated","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A high performance 16-Mb DRAM technology\",\"authors\":\"P. Bakeman, A. Bergendahl, M. Hakey, D. Horak, S. Luce, B. Pierson\",\"doi\":\"10.1109/VLSIT.1990.110983\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstrated\",\"PeriodicalId\":441541,\"journal\":{\"name\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"volume\":\"91 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1990.110983\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.110983","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor node to the transfer device, and smoothed dep/etched phosphosilicate glass (PSG) passivation. The application of the above technology elements in conjunction with the MINT cell structure makes it possible to achieve a DRAM cell size of 4.13 μm2, using six 0.5-μm critical-dimension and 0.2-μm overlay lithography levels. Up to ten sequential process steps are performed in a single cluster. A 50-ns access time has been demonstrated
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