Process technologies for a 16 ns high speed 1 Mb CMOS EPROM

An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability. Process and device parameters are summarized. An 0.8-μm N-well CMOS, 1 poly Si+1 MoSi polycide double metal technology is used. To fabricate 5-V and 12.5-V high-voltage NMOS and PMOS transistors simultaneously, masked lightly-doped-drain structures are used