New well structure for deep sub-μm CMOS/BiCMOS using thin epitaxy over buried layer and trench isolation

Abstract

Deep submicrometer CMOS devices having a novel well structure using thin epitaxy over a buried n+ layer, a p-type substrate, and trench isolation are proposed. Good isolation characteristics and high latchup immunity are obtained. The thin epitaxial layer, which is necessary for on-chip high-performance bipolar devices, lowers the voltage tolerance of the parasitic vertical bipolar, and causes a new type of latchup phenomena. This must be taken into consideration in p-well design. One-eighth-frequency dividers fabricated to evaluate the new well structure can function up to a maximum operating frequency of 4.2 GHz at 3 V of supply voltage