D. Moy, L.K. Wang, D. Seeger, J. Silverman, C. Hu, F. Kaufman, A. Ray, M. Jaso, N. Mazzeo
{"title":"采用x射线光刻技术制备的0.5 μ m全尺度双能级金属全平面互连结构","authors":"D. Moy, L.K. Wang, D. Seeger, J. Silverman, C. Hu, F. Kaufman, A. Ray, M. Jaso, N. Mazzeo","doi":"10.1109/VLSIT.1990.110982","DOIUrl":null,"url":null,"abstract":"A fully planarized two-level-metal structure has been successfully fabricated at 0.5 μm groundrules with the use of X-ray lithography at all processing levels. A 0.5-μm minimum feature size was required for all levels, including the second-level metal. Planarized PECVD oxide and PECVD nitride were employed as dual dielectric layers below M1 and M2. Chemical vapor deposition (CVD) W studs formed by W etchback served as vertical connections for interlevel vias and contacts. All ten lithography patterning steps were performed with X-ray exposures to determine what possible implications this emerging technology might have on the implementation of the interconnect levels","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography\",\"authors\":\"D. Moy, L.K. Wang, D. Seeger, J. Silverman, C. Hu, F. Kaufman, A. Ray, M. Jaso, N. Mazzeo\",\"doi\":\"10.1109/VLSIT.1990.110982\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully planarized two-level-metal structure has been successfully fabricated at 0.5 μm groundrules with the use of X-ray lithography at all processing levels. A 0.5-μm minimum feature size was required for all levels, including the second-level metal. Planarized PECVD oxide and PECVD nitride were employed as dual dielectric layers below M1 and M2. Chemical vapor deposition (CVD) W studs formed by W etchback served as vertical connections for interlevel vias and contacts. All ten lithography patterning steps were performed with X-ray exposures to determine what possible implications this emerging technology might have on the implementation of the interconnect levels\",\"PeriodicalId\":441541,\"journal\":{\"name\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1990.110982\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.110982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography
A fully planarized two-level-metal structure has been successfully fabricated at 0.5 μm groundrules with the use of X-ray lithography at all processing levels. A 0.5-μm minimum feature size was required for all levels, including the second-level metal. Planarized PECVD oxide and PECVD nitride were employed as dual dielectric layers below M1 and M2. Chemical vapor deposition (CVD) W studs formed by W etchback served as vertical connections for interlevel vias and contacts. All ten lithography patterning steps were performed with X-ray exposures to determine what possible implications this emerging technology might have on the implementation of the interconnect levels