0.6 μm, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications

Abstract

An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition to silicided poly for local interconnection, this technology offers four layers of metallization with chemical vapor deposition (CVD) tungsten-filled contacts and vias. Interconnection delays are 1 ps/mil. ABiC technology is most attractive for high-performance 50K to 100K gate ECL logic arrays, 100K to 200K gate CMOS/BiCMOS logic arrays, and high-density ASIC products requiring embedded memories