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Digest of Technical Papers.1990 Symposium on VLSI Technology最新文献

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A new SOL fabrication technique for ultrathin active layer of less than 80 nm 一种制备小于80nm的超薄活性层的溶胶制备新技术
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111024
H. Horie, K. Oikawa, H. Ishiwari, T. Yamazaki, S. Ando
{"title":"A new SOL fabrication technique for ultrathin active layer of less than 80 nm","authors":"H. Horie, K. Oikawa, H. Ishiwari, T. Yamazaki, S. Ando","doi":"10.1109/VLSIT.1990.111024","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111024","url":null,"abstract":"A silicon-on-insulator (SOI) technique has been developed for fabricating thin-film SOI transistors. Ultrathin high-quality SOI less than 80 nm thick has been produced by the technique, which was named HO/SOI (Hollowed-Out SOI). A submicron p-MOSFET has been formed by this technique. The transconductance gm of the SOI MOSFET is 0.75 mS/mm at a gate voltage of -5 V and a drain voltage of -0.05 V. The g m is 47% higher than that of a bulk MOSFET. Negative differential conductance was observed for the p-MOSFET, as had been previously observed in n-MOSFET. The technique makes it possible to control the thermal oxide thickness of back gates, and eliminate leakage on the back surface of an SOI. This leads to the SOI transistor controlled by both side gates, or upside gate and bottom side gate","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132482754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise 利用随机电报噪声表征亚微米MOSFET中单个热电子感应阱
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110996
P. Fang, K. Hung, P. Ko, C. Hu
{"title":"Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise","authors":"P. Fang, K. Hung, P. Ko, C. Hu","doi":"10.1109/VLSIT.1990.110996","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110996","url":null,"abstract":"Individual interface traps generated by hot-electron stress were observed for the first time. Single trap filling and emptying can cause 0.1% step noise in drain current due to coulombic scattering. Trap location (3-10 Å from interface), time constant, energy and escape frequency are found to be very different from pre-stress (process-induced) traps. Random telegraph (RTS) noise was found to be a useful tool for studying stress-induced interface traps. It is more easily observable for stress-induced traps than process-induced traps due to the small stress area and low stress-induced trap density after light stressing. Using RTS as a characterization tool, it was found that the stress-induced traps are located closer to the interface, and therefore have a shorter time constant and much stronger influence on scattering and ΔId than process-induced traps. RTS only reveals those traps near the Fermi level, while the DC MOSFET IV degradation is also influenced by all the charged traps","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126608130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Mobile ion gettering in passivated p+ polysilicon gates 钝化p+多晶硅栅极中的移动离子捕集
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111039
C. Wong, C. Hsu, Y. Taur
{"title":"Mobile ion gettering in passivated p+ polysilicon gates","authors":"C. Wong, C. Hsu, Y. Taur","doi":"10.1109/VLSIT.1990.111039","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111039","url":null,"abstract":"Mobile ion contamination in the deep-submicron regime was studied for boron, arsenic, and phosphorus-doped polysilicon gates. An effective gettering process is presented for the passivation of p+ polysilicon gates without boron penetration through thin gate oxide. The issue of mobile ion gettering with p+ polysilicon in deep-submicron CMOS technology is also studied. A channel-length-dependent mobile ion instability was observed for the first time. A gettering/passivation process using polysilicon gates (PSG/LTO) with proper activation anneals was found to be effective for p+ polysilicon gated devices without causing boron penetration through the gate oxide","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123075175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Continuous diagnosis of low-pressure chemical vapor deposition reactors using evidence integration 基于证据集成的低压化学气相沉积反应器的连续诊断
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111028
N. Chang, C. Spanos
{"title":"Continuous diagnosis of low-pressure chemical vapor deposition reactors using evidence integration","authors":"N. Chang, C. Spanos","doi":"10.1109/VLSIT.1990.111028","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111028","url":null,"abstract":"A diagnostic system is presented that uses the Dempster-Shafer (D-S) evidential reasoning theory to conduct real-time malfunction diagnosis on semiconductor processing equipment. This is accomplished by combing the continuous stream of information that originates from maintenance status records, from real-time sensor measurements, and from the differences between inline measurements and values predicted by equipment models. The effectiveness of this technique is demonstrated on an low-pressure chemical vapor deposition (LPCVD) reactor used for the deposition of undoped polysilicon","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121566488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A spill over effect of avalanche generated electrons in buried pMOSFETs 埋藏式pmosfet中雪崩产生的电子溢出效应
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111013
A. Hiroki, S. Odanaka, T. Morii
{"title":"A spill over effect of avalanche generated electrons in buried pMOSFETs","authors":"A. Hiroki, S. Odanaka, T. Morii","doi":"10.1109/VLSIT.1990.111013","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111013","url":null,"abstract":"Hot carrier effects of a buried pMOSFET in the retrograde n-well have been investigated. A new phenomenon, a spill-over effect of avalanche-generated electrons into the bulk, was discovered. This effect is inherent in pMOSFETs fabricated in the n-well with high doping. It is shown that the effect reduces the hot-electron-induced device degradation even with high hot-electron generation","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133214362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
KrF excimer laser lithography with high sensitivity positive resist and high power laser 高灵敏度正阻高功率激光KrF准分子激光光刻技术
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110981
Y. Tani, M. Sasago, N. Momura, H. Fujimoto, N. Furuya, T. Ono, N. Horiuchi, T. Miyata
{"title":"KrF excimer laser lithography with high sensitivity positive resist and high power laser","authors":"Y. Tani, M. Sasago, N. Momura, H. Fujimoto, N. Furuya, T. Ono, N. Horiuchi, T. Miyata","doi":"10.1109/VLSIT.1990.110981","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110981","url":null,"abstract":"A positive resist with high sensitivity and stability named ASKA (Alkaline Soluble Kinematics using Acid generator) is described. A KrF excimer laser with a maximum laser power of 8.8 W and more than 109 pulses named PCR (polarization coupled resonator) is also presented. The result of KrF excimer laser lithography for 0.4-μm VLSI using this combination of ASKA and PCR technologies indicates improved throughput over conventional g-line lithography","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133439146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Non-invasive silicon temperature measurement by infrared transmission for rapid thermal processing applications 非侵入式硅温度测量红外传输快速热加工应用
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111031
J. Sturm, P. Schwartz, P. Garone
{"title":"Non-invasive silicon temperature measurement by infrared transmission for rapid thermal processing applications","authors":"J. Sturm, P. Schwartz, P. Garone","doi":"10.1109/VLSIT.1990.111031","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111031","url":null,"abstract":"A method for the noninvasive measurement of silicon wafer temperature based on infrared transmission is presented. The method is well suited to the 400-800°C temperature range, can be used through thick quartz walls, and is compatible with rapid thermal processing and epitaxial growth. The approach relies on the decreased bandgap, higher phonon population, and increased free carrier concentrations in silicon at elevated temperatures. These effects cause increased optical absorption in the infrared (near band-edge) region due to both increased band-to-band and intraband absorption. By measuring the infrared optical transmission of the wafer in situ during processing, an intimate measure of the wafer temperature can be attained. Improved control of silicon-germanium film growth has been demonstrated","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132220305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high speed and high reliability MOSFET utilizing an auxiliary gate 采用辅助栅极的高速高可靠性MOSFET
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110998
M. Minami, Y. Sawahata, H. Matsuki, T. Nagano
{"title":"A high speed and high reliability MOSFET utilizing an auxiliary gate","authors":"M. Minami, Y. Sawahata, H. Matsuki, T. Nagano","doi":"10.1109/VLSIT.1990.110998","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110998","url":null,"abstract":"For future submicron MOSFETs, the realization of both high speed and high reliability is becoming more and more difficult. A conventional LDD structure is not adequately reliable for future submicron MOSFETs due to the high electric field in the vicinity of the drain junction. To decrease the electric field, gate-overlap LDD (GOLDD) structures have been proposed. However, these structures have larger gate-drain and gate-source overlap capacitance which results in a slow circuit speed. This research demonstrates a novel auxiliary-gate lightly-doped-drain (AGLDD) structure which realizes high speed and high reliability simultaneously","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133332612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
BiCMOS gate performance optimization using a unified delay model 基于统一延迟模型的BiCMOS栅极性能优化
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.111023
P. Raje, K. Cham, K. Saraswat
{"title":"BiCMOS gate performance optimization using a unified delay model","authors":"P. Raje, K. Cham, K. Saraswat","doi":"10.1109/VLSIT.1990.111023","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.111023","url":null,"abstract":"A unified delay model is presented that predicts BiCMOS gate delay for both long- and short-channel MOSFETs, in low-level and high-level injection in the bipolar junction transistors (BJTs), for 5 V and reduced supply and over a wide range of circuit parameter variation. The model is applied to devise circuit and device design strategies to optimize gate performance at 5 V and at scaled supply voltage. The model predicts analytical expressions for an optimum BJT emitter length versus MOS gate width for which the delay is a minimum. To minimize performance degradation at reduced supply, an effective circuit strategy is to design with wide MOS devices and small-length BJTs. The crucial BJT parameters are (reduced) junction capacitance, (reduced) transit time and the gain-knee current product. For the MOSFET the saturation current must be maximized and gate length scaling is desirable as long as the saturation current increases","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130719233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A highly reliable 0.3 μm n-channel MOSFET using poly spacers 一个高度可靠的0.3 & μ m n沟道MOSFET，采用多聚间隔片
Digest of Technical Papers.1990 Symposium on VLSI Technology Pub Date : 1990-06-04 DOI: 10.1109/VLSIT.1990.110997
I. Chen, J.P. Lin, C. Teng
{"title":"A highly reliable 0.3 μm n-channel MOSFET using poly spacers","authors":"I. Chen, J.P. Lin, C. Teng","doi":"10.1109/VLSIT.1990.110997","DOIUrl":"https://doi.org/10.1109/VLSIT.1990.110997","url":null,"abstract":"A reliable 0.3-μm n-channel gate-to-drain overlapped MOSFET was realized using poly spacers and demonstrated to have more than a 10-year lifetime at 3.5 V operation. This is more than two orders of magnitude longer than the conventional oxide-spacer lightly-doped-drain (LDD) devices. The large improvement is due to the unfavorable oxide field, when gate voltage (VG) is less than or equal to drain voltage (VD), for electron trapping into the gate-drain overlap region and not to the reduction of channel electric field. Under unusual operations with VG>VD the poly-spacer devices have a few times larger gate current, and thus more serious degradation, than the oxide-spacer devices. The drawbacks of the poly-space device, larger CGD and weaker gate oxide integrity can be significantly improved by a short oxidation before the poly-spacer formation. The optimum LDD dosage to avoid spacer-induced degradation is close to the highest dose before punch-through occurs. The hot-electron immunity, process simplicity and compatibility with the oxide-spacer technology make this poly-spacer device a viable approach in the deep-submicron regime","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"1981 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130925050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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