A new SOL fabrication technique for ultrathin active layer of less than 80 nm

A silicon-on-insulator (SOI) technique has been developed for fabricating thin-film SOI transistors. Ultrathin high-quality SOI less than 80 nm thick has been produced by the technique, which was named HO/SOI (Hollowed-Out SOI). A submicron p-MOSFET has been formed by this technique. The transconductance gm of the SOI MOSFET is 0.75 mS/mm at a gate voltage of -5 V and a drain voltage of -0.05 V. The g m is 47% higher than that of a bulk MOSFET. Negative differential conductance was observed for the p-MOSFET, as had been previously observed in n-MOSFET. The technique makes it possible to control the thermal oxide thickness of back gates, and eliminate leakage on the back surface of an SOI. This leads to the SOI transistor controlled by both side gates, or upside gate and bottom side gate