{"title":"A highly reliable 0.3 μm n-channel MOSFET using poly spacers","authors":"I. Chen, J.P. Lin, C. Teng","doi":"10.1109/VLSIT.1990.110997","DOIUrl":null,"url":null,"abstract":"A reliable 0.3-μm n-channel gate-to-drain overlapped MOSFET was realized using poly spacers and demonstrated to have more than a 10-year lifetime at 3.5 V operation. This is more than two orders of magnitude longer than the conventional oxide-spacer lightly-doped-drain (LDD) devices. The large improvement is due to the unfavorable oxide field, when gate voltage (VG) is less than or equal to drain voltage (VD), for electron trapping into the gate-drain overlap region and not to the reduction of channel electric field. Under unusual operations with VG>VD the poly-spacer devices have a few times larger gate current, and thus more serious degradation, than the oxide-spacer devices. The drawbacks of the poly-space device, larger CGD and weaker gate oxide integrity can be significantly improved by a short oxidation before the poly-spacer formation. The optimum LDD dosage to avoid spacer-induced degradation is close to the highest dose before punch-through occurs. The hot-electron immunity, process simplicity and compatibility with the oxide-spacer technology make this poly-spacer device a viable approach in the deep-submicron regime","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"1981 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.110997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A reliable 0.3-μm n-channel gate-to-drain overlapped MOSFET was realized using poly spacers and demonstrated to have more than a 10-year lifetime at 3.5 V operation. This is more than two orders of magnitude longer than the conventional oxide-spacer lightly-doped-drain (LDD) devices. The large improvement is due to the unfavorable oxide field, when gate voltage (VG) is less than or equal to drain voltage (VD), for electron trapping into the gate-drain overlap region and not to the reduction of channel electric field. Under unusual operations with VG>VD the poly-spacer devices have a few times larger gate current, and thus more serious degradation, than the oxide-spacer devices. The drawbacks of the poly-space device, larger CGD and weaker gate oxide integrity can be significantly improved by a short oxidation before the poly-spacer formation. The optimum LDD dosage to avoid spacer-induced degradation is close to the highest dose before punch-through occurs. The hot-electron immunity, process simplicity and compatibility with the oxide-spacer technology make this poly-spacer device a viable approach in the deep-submicron regime
一个可靠的0.3 μ m n沟道栅极漏极重叠MOSFET使用聚间隔实现,并证明在3.5 V工作下具有超过10年的寿命。这比传统的氧化物间隔剂轻掺杂漏极(LDD)器件长两个数量级以上。当栅极电压小于或等于漏极电压时,氧化场不利于电子捕获到栅极-漏极重叠区,而不是通道电场的减小。在不寻常的VG>VD操作下,多间隔器器件的栅极电流比氧化物间隔器器件大几倍,因此劣化更严重。在聚间隔层形成之前进行短时间的氧化,可以显著改善多空间器件的缺陷,即较大的CGD和较弱的栅极氧化物完整性。避免间隔剂诱导降解的最佳LDD剂量接近穿孔前的最高剂量。热电子抗扰性、工艺简单以及与氧化物间隔层技术的兼容性使该多间隔层器件成为深亚微米领域的一种可行方法