{"title":"Characterizing a single hot-electron-induced trap in submicron MOSFET using random telegraph noise","authors":"P. Fang, K. Hung, P. Ko, C. Hu","doi":"10.1109/VLSIT.1990.110996","DOIUrl":null,"url":null,"abstract":"Individual interface traps generated by hot-electron stress were observed for the first time. Single trap filling and emptying can cause 0.1% step noise in drain current due to coulombic scattering. Trap location (3-10 Å from interface), time constant, energy and escape frequency are found to be very different from pre-stress (process-induced) traps. Random telegraph (RTS) noise was found to be a useful tool for studying stress-induced interface traps. It is more easily observable for stress-induced traps than process-induced traps due to the small stress area and low stress-induced trap density after light stressing. Using RTS as a characterization tool, it was found that the stress-induced traps are located closer to the interface, and therefore have a shorter time constant and much stronger influence on scattering and ΔId than process-induced traps. RTS only reveals those traps near the Fermi level, while the DC MOSFET IV degradation is also influenced by all the charged traps","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.110996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Individual interface traps generated by hot-electron stress were observed for the first time. Single trap filling and emptying can cause 0.1% step noise in drain current due to coulombic scattering. Trap location (3-10 Å from interface), time constant, energy and escape frequency are found to be very different from pre-stress (process-induced) traps. Random telegraph (RTS) noise was found to be a useful tool for studying stress-induced interface traps. It is more easily observable for stress-induced traps than process-induced traps due to the small stress area and low stress-induced trap density after light stressing. Using RTS as a characterization tool, it was found that the stress-induced traps are located closer to the interface, and therefore have a shorter time constant and much stronger influence on scattering and ΔId than process-induced traps. RTS only reveals those traps near the Fermi level, while the DC MOSFET IV degradation is also influenced by all the charged traps