B. Riemenschneider, A. Esquivel, J. Paterson, M. Gill, S. Lin, J. Schreck, D. McElroy, P. Truong, R. Bussey, B. Ashmore, M. McConnell, H. Stiegler, P. Shah
{"title":"具有8.6 UM2单元的5伏仅4mb闪存EEPROM的工艺技术","authors":"B. Riemenschneider, A. Esquivel, J. Paterson, M. Gill, S. Lin, J. Schreck, D. McElroy, P. Truong, R. Bussey, B. Ashmore, M. McConnell, H. Stiegler, P. Shah","doi":"10.1109/VLSIT.1990.111040","DOIUrl":null,"url":null,"abstract":"A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 μm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 μm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 μm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle","PeriodicalId":441541,"journal":{"name":"Digest of Technical Papers.1990 Symposium on VLSI Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cell\",\"authors\":\"B. Riemenschneider, A. Esquivel, J. Paterson, M. Gill, S. Lin, J. Schreck, D. McElroy, P. Truong, R. Bussey, B. Ashmore, M. McConnell, H. Stiegler, P. Shah\",\"doi\":\"10.1109/VLSIT.1990.111040\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 μm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 μm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 μm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle\",\"PeriodicalId\":441541,\"journal\":{\"name\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers.1990 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1990.111040\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers.1990 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1990.111040","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
介绍了一种单晶体管先进的非接触EEPROM (ACEE)阵列技术，该技术具有8.6 μm2单元，用于单电源5v仅4mb闪存EEPROM。该ACEE技术具有0.8 μ m的最小光刻特征尺寸和一种新颖的亚光刻远程隧道二极管结构。通过二极管隔离，实现了同一单元位线之间的低压隔离，有效间隔为0.65 μ m;相邻单元位线之间的高压隔离依赖于LOCOS隔离。集成的工艺流程成功地将ACEE阵列和18v操作(2.0 μ m, 18v n通道，15v p通道)的工艺增强合并到具有硅化触点的核心5-V 0.8 μ m CMOS工艺中。该单元已在全电路4mb闪存EEPROM VLSI车辆上进行了演示
A process technology for a 5-volt only 4 Mb flash EEPROM with an 8.6 UM2 cell
A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation at an effective separation of 0.65 μm; the high-voltage isolation between bitlines of adjacent cells depends on LOCOS isolation. The integrated process flow has successfully merged both the ACEE array and process enhancements for 18-V operation (2.0 μm, 18 V N-channel, 15 V P-channel) into a core 5-V 0.8 μm CMOS process with silicided contacts. This cell has been demonstrated on a full-circuit 4-Mb flash EEPROM VLSI vehicle
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