A fundamental performance limit of optimized 3.3 V subquarter micron fully overlapped LDD MOSFETs

Abstract

This research reports the direct experimental quantification of the relationship between gate-to-drain capacitance (Cgd) and hot-electron reliability (HER) for fully overlapped lightly-doped-drain (FOLD) n-channel MOSFETs (NFETs). Based on this result it is shown that a peak in device performance occurs at an effective channel length of approximately 0.22 μm for reliable 3.3 V FOLD NFETs having a gate oxide thickness of 10 nm. Below 0.22 μm, performance actually decreases due to the addition of the very large (LDD) regions (fingers) required to maintain adequate HER. This peak shifts to an effective channel length of ≈0.15 μm for asymmetric 3.3-V-FOLD NFETs. Despite this performance limit, it is found that 3.3 V FOLD NFETs are still faster than scaled 2.5-V single-diffusion NFETs down to 0.25 μm. Although a significant performance advantage has been reported for FOLD n-channel MOSFETs, the fundamental tradeoff between parasitic gate-to-drain capacitance and hot electron reliability inherent to the FOLD structure has yet to be quantified. This tradeoff is of critical importance since it limits the performance of FOLD NFETs