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Digest of Papers IEEE International Workshop on IDDQ Testing最新文献

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On-line CMOS BICS: an experimental study 在线CMOS BICS的实验研究
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633019
Y. Maidon, Y. Deval, F. Verdier, J. Bégueret, J. Dom
{"title":"On-line CMOS BICS: an experimental study","authors":"Y. Maidon, Y. Deval, F. Verdier, J. Bégueret, J. Dom","doi":"10.1109/IDDQ.1997.633019","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633019","url":null,"abstract":"A CMOS built-in current sensor is proposed. It is dedicated to mixed signal circuits power supply current monitoring. It takes advantage of a parasitic resistor, so its implementation is very transparent. Measurement results of a manufactured test chip highlight the behaviors of the sensor in terms of linearity, speed and noise.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125155065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high-speed low-voltage built-in current sensor 一种高速低压内置电流传感器
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633020
Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee
{"title":"A high-speed low-voltage built-in current sensor","authors":"Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee","doi":"10.1109/IDDQ.1997.633020","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633020","url":null,"abstract":"This paper presents a high-speed low-voltage built-in current sensor. It mainly utilizes a bulk-driven current mirror as a current sensor to reduce the power supply voltage drop. Based on this technique, we develop an analytic and empirical model to design the built-in current sensor. Experimental results show that the bulk-driven built-in current sensor can have high speed and low area overhead under a low power supply voltage.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121697435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
STEM: a framework for simulating and selecting I/sub DDQ/ measurement points for leakage faults 用于模拟和选择泄漏故障的I/sub DDQ/测量点的框架
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633014
S. Chakravarty, S. Zachariah, P. J. Thadikaran
{"title":"STEM: a framework for simulating and selecting I/sub DDQ/ measurement points for leakage faults","authors":"S. Chakravarty, S. Zachariah, P. J. Thadikaran","doi":"10.1109/IDDQ.1997.633014","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633014","url":null,"abstract":"An efficient algorithm, named state transition based method (STEM), for simulating I/sub DDQ/ tests for leakage faults is presented. It also provides an efficient framework for \"incremental fault simulation\" which is embedded in the problem of selecting optimal I/sub DDQ/ measurement points for leakage faults, STBM can be used for both combinational and sequential circuits. Experimental results show that STEM outperforms all known fault simulation algorithms and optimal loop measurement point selection algorithms for leakage faults.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128585034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A design for test proposal for improving dynamic current testing reliability on regenerative sense amplifiers 一种提高再生传感放大器动态电流测试可靠性的测试方案设计
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633009
S. Bracho
{"title":"A design for test proposal for improving dynamic current testing reliability on regenerative sense amplifiers","authors":"S. Bracho","doi":"10.1109/IDDQ.1997.633009","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633009","url":null,"abstract":"A design for test method for improving dynamic supply current testing reliability on regenerative sense amplifier structures is described in this paper. This proposal uses a built-in current monitor to represent the supply current through the regenerative sense amplifier by a digital signature, externally analyzed by a digital tester. A fully differential fast comparator circuit has been used as a demonstrator to explore the effectiveness of the proposal. Different catastrophic faults at transistor level were considered and simulation results are discussed.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability, test, and I/sub DDQ/ measurements 可靠性、测试和I/sub DDQ/测量
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633021
C. Hawkins, A. Keshavarzi, J. Soden
{"title":"Reliability, test, and I/sub DDQ/ measurements","authors":"C. Hawkins, A. Keshavarzi, J. Soden","doi":"10.1109/IDDQ.1997.633021","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633021","url":null,"abstract":"I/sub DDQ/ measurements are strongly identified with CMOS IC testing, however I/sub DDQ/ also has long term links to IC reliability. This paper overviews the association of reliability and I/sub DDQ/ testing. Three reliability topics are discussed: fundamental failure mechanisms, the relation of I/sub DDQ/ to burn-in, and the use of test data to predict reliability performance.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"1993 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125539477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Simulation of logic/IDDQ tests for resistive shorts in logic circuits by using simplicial approximation 用简单近似法模拟逻辑电路中电阻性短路的逻辑/IDDQ测试
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633024
Hung-Jen Lin, L. Milor
{"title":"Simulation of logic/IDDQ tests for resistive shorts in logic circuits by using simplicial approximation","authors":"Hung-Jen Lin, L. Milor","doi":"10.1109/IDDQ.1997.633024","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633024","url":null,"abstract":"Logic circuits in the presence of resistive shorts often exhibit analog behavior which can be computationally expensive to simulate. This paper introduces a numerical method called simplicial approximation for its application to simulation of logic/IDDQ tests for resistive shorts. Example circuits with transistor gate-to-drain and gate-to-source shorts are used to demonstrate the feasibility of the method. The results, when compared to SPICE simulation, show a 95% reduction in computational time at the price of less numerical accuracy, which is generally acceptable in this application.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An approach for detecting bridging fault-induced delay faults in static CMOS circuits using dynamic power supply current monitoring 基于动态电源电流监测的静态CMOS电路桥接故障延迟故障检测方法
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633017
A. Walker, P. Lala
{"title":"An approach for detecting bridging fault-induced delay faults in static CMOS circuits using dynamic power supply current monitoring","authors":"A. Walker, P. Lala","doi":"10.1109/IDDQ.1997.633017","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633017","url":null,"abstract":"A new approach for the detection of bridging fault-induced delay faults in static CMOS logic circuits is presented in this paper. It is based upon the transient current that is sourced (or sink) by the power supply (or ground) rail of a primary output gate during a low-to-high (or high-to-low) output transition. We show that the dynamic power supply current (DPSC) can be used to detect delay faults that are due to bridging faults because the DPSC is a function of the parameters and the interconnectivity of the transistors that form the discharge/charge circuits in the gates along the path-under-test. An example of a dynamic power supply current monitoring circuit is also presented. The paper is concluded with an example of the application of the proposed approach for detecting bridging faults in static CMOS logic circuit.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129991169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
I/sub DDQ/ testable dynamic PLAs I/sub DDQ/可测试动态pla
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633007
M. Sachdev, H. Kerkhoff
{"title":"I/sub DDQ/ testable dynamic PLAs","authors":"M. Sachdev, H. Kerkhoff","doi":"10.1109/IDDQ.1997.633007","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633007","url":null,"abstract":"Testing of bridging faults in PLAs by means of voltage testing is expensive. However, same can be done efficiently with I/sub DDQ/ testing. In this article we propose two I/sub DDQ/ testable PLA configurations. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. All likely bridging faults in these configurations are tested efficiently by the I/sub DDQ/ test technique. Such a test is independent of the function implemented in a PLA.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"135 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113980649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A simulation-based method for estimating defect-free I/sub DDQ/ 基于仿真的无缺陷I/sub DDQ/估算方法
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633018
P. Maxwell, J. Rearick
{"title":"A simulation-based method for estimating defect-free I/sub DDQ/","authors":"P. Maxwell, J. Rearick","doi":"10.1109/IDDQ.1997.633018","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633018","url":null,"abstract":"This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifier transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual I/sub DDQ/ value. SPICE simulation results are also presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"375 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122168075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Estimation of partition size for I/sub DDQ/ testing using built-in current sensing 估计分区大小的I/sub DDQ/测试使用内置电流传感
Digest of Papers IEEE International Workshop on IDDQ Testing Pub Date : 1997-11-05 DOI: 10.1109/IDDQ.1997.633016
S. Menon, M. Palmgren
{"title":"Estimation of partition size for I/sub DDQ/ testing using built-in current sensing","authors":"S. Menon, M. Palmgren","doi":"10.1109/IDDQ.1997.633016","DOIUrl":"https://doi.org/10.1109/IDDQ.1997.633016","url":null,"abstract":"I/sub DDQ/ testing of CMOS circuits can detect faults that are not easily detected using traditional test techniques. The quiescent current drawn by CMOS devices is very small, and certain faults in a device may cause this current to increase by several orders of magnitude. Current sensors are used to detect abnormalities in the quiescent current. The quiescent current in a circuit can be monitored using an external current sensor or a Built-in Current Sensor (BICS). BICS show improvement in speed and resolution over external current sensors. When connecting a BICS to a circuit, the site of the partition, propagation delay and settling time of the circuit must be taken into consideration. Variations in process parameters may cause variations in the fault-free and faulty I/sub DDQ/ in a CMOS device. As the number of gates in a device increase, the distributions of fault-free and faulty I/sub DDQ/ may start to overlap, thus making it impassible to distinguish between fault-free and faulty currents in a device. Adding a BICS to a circuit may increase the settling time of the circuit, due to the lumped capacitance across the BICS. Monte Carlo simulations have been performed on circuits of various sizes and levels to estimate the partition size for I/sub DDQ/ testing using BICS.","PeriodicalId":429650,"journal":{"name":"Digest of Papers IEEE International Workshop on IDDQ Testing","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121507946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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